Recently, Apple has been reported to be evaluating a return to the commercial server market, with proposed products targeting AI inference and considering the use of its own M-series chips, as well as evaluating the introduction of NVIDIA's NVLink Fusion interconnect technology.

Apple has previously used its self-developed chips for private cloud computing, handling cloud tasks for Apple Intelligence. If servers are to be sold to external customers, the products would need to enter other enterprises' data centers, integrating with clients' networks, software, and operational systems. For a company with chip design capabilities, commercial servers still represent a business that requires organizing an external supply chain.

In the following week, interconnect suppliers successively disclosed new developments. On September 23, Cadence announced a demonstration of the UALink solution on TSMC's N3P process, providing silicon-validated interface designs for chip companies adopting open interconnects. On the same day, network chip company Cornelis further introduced its product roadmap for next-generation AI systems, planning to offload some data processing to network cards and switching chips.

Entering the server market with self-developed chips requires deciding on an interconnect system and finding partners capable of providing interfaces, switching, and connectivity components. Recent disclosures on interface validation, product roadmaps, and sampling plans revolve around these procurement choices.

01 Switch Market: Generational Upgrades and Capacity Expansions in Parallel

IDC's statistics released on September 11 show that global data center Ethernet switch market revenue reached $12.3 billion in the second quarter of 2026, a year-on-year increase of 64.5%. This figure, covering switch equipment for hyperscale, service provider, and enterprise data centers, reflects significant procurement demand for data exchange between servers.

In the same statistics, the proportion of 800GbE products in data center Ethernet switch revenue rose from 35.9% in the first quarter to 41.2% in the second quarter. As the market grows, revenue is also concentrating on products with higher port speeds. After switch port speed upgrades, matching switching chips and connectivity components must also meet new signal transmission requirements.

Dell'Oro's report on September 3 noted that switch sales for AI backend networks surpassed those of frontend networks for the first time in the second quarter. Frontend networks handle business access and other communications, while backend networks primarily connect acceleration servers, serving the extensive data exchange during training and inference. Dedicated networks for computing tasks are altering the structure of data center network procurement.

Within the AI backend Ethernet segment, 800G devices accounted for the majority of shipments and revenue in the quarter, with 1.6T products beginning sampling and expected to expand shipments in the second half of the year. Current procurement and next-generation validation are occurring simultaneously, requiring suppliers to ensure existing equipment delivery while preparing new products for clients' next system designs. The alignment of R&D timelines with clients' expansion schedules directly impacts which procurement rounds products can participate in.

Connecting accelerators and switching equipment also requires cables, optical interconnect components, and chips for restoring high-speed signals. Credo sells such products. On September 1, the company announced its latest quarterly results ending August 1, with overall revenue reaching $479 million, a year-on-year increase of 114.7%. These connectivity products have become a sizable business within the server supply chain.

Credo's products cover both copper and optical connections, as well as forms such as chips, modules, and cables. The choice of computing chip in a server does not eliminate corresponding connectivity needs; however, each generation of systems uses different transmission distances, interfaces, and cabling methods, altering specific component combinations. Therefore, independent suppliers must develop products in line with clients' overall machine designs, vying for new customers while maintaining existing system projects.

Dell'Oro expects the AI backend switch market to remain supply-constrained for at least the next one to two years. This provides conditions for vendors with delivery capabilities to expand their business and makes buyers prioritize equipment availability. Even if a cluster has secured acceleration cards, it cannot operate at the intended scale without completed network matching ; the delivery schedule of interconnect components must align with server procurement.

The firm also predicts that Ethernet sales for AI backends currently primarily come from cross-server, cross-cluster connections, with applications for tighter accelerator interconnects emerging from the second half of the year. Suppliers can compete for product positions extending into rack interiors, addressing not just faster data transmission but also how accelerators exchange results and collaborate on tasks.

02 Self-Developed Chips: What Interconnect Support is Needed?

Within a server or a group of tightly collaborating accelerators, chips require higher bandwidth and low-latency connections. Apple's evaluated NVLink Fusion and Cadence's validated UALink relate to this level of demand. They determine the interconnect system for accelerators, with interface IP, switching chips, and connectivity components implementing the system in products.

On September 10, d-Matrix announced that its next-generation Raptor chip would adopt NVLink Fusion and incorporate NVIDIA's MGX rack design, with shipments expected to begin in the fourth quarter of 2027. The company focuses on inference chips, delegating some interconnect and rack design to established platforms. For companies taking this approach, product development must align with the platform's interface, system design, and validation requirements.

UALink offers another way to organize the supply chain. It is an accelerator interconnect standard that chip design companies can adopt, collaborating with corresponding switching chip and system vendors. Cadence provides IP as pre-designed modules integrable into client chips; silicon validation on specified processes reduces clients' efforts to implement protocols from scratch.

Such interface designs are directly related to manufacturing processes. For companies preparing for tape-out, standard openness is just one condition; they must also consider available IP for the target process and whether switching chips can keep pace with overall machine development. Cadence's disclosed progress on the N3P process provides specific chip design conditions, still requiring validation within clients' complete products.

Once an interface is incorporated into chip design, subsequent changes necessitate adjustments to chips, packaging, and boards. Thus, interconnect vendors typically compete for clients earlier than formal server procurement. Products participating in definition and validation are more likely to enter the bill of materials for this generation of systems; other suppliers, even with similarly performing products launched later, must reacquire clients' design and validation resources.

Complete machine vendors are also arranging products for different routes. On September 23, New H3C introduced an architecture using UALink within racks and Ethernet between racks at the Yunqi Conference forum: first organizing multiple accelerators into tightly collaborating computing units, then connecting these units into larger clusters. The company also stated that its UniPoD S80000 series would follow various mainstream interconnect protocols, preserving options for different chip combinations.

A single standard can reduce redundant designs but does not mean accelerator cards from different vendors can be directly mixed. As mentioned at the conference by New H3C, the coexistence of multiple chips and interconnect protocols increases cross-vendor adaptation costs. Beyond interfaces, drivers, communication software, and fault handling must also be validated together. As server buyers' choices expand, system vendors must maintain more software and hardware combinations.

For companies planning to use self-developed chips, joining existing platforms allows reuse of established matching ; adopting open standards and selecting suppliers independently retains more combination flexibility while undertaking more integration work. Both sides compete for next-generation server designs, with clients comparing overall scheme performance, cost, and delivery schedules.

03 Independent Suppliers: Vying for Next-Generation Servers

Cornelis announced $205 million in financing on September 14, to be used for product expansion, production, and customer deployment. The company's network technology is already used in hundreds of data centers, with CN5000 currently shipping and CN6000 sampling to clients, expected to expand supply in the fourth quarter. Entering the rack internal interconnect market requires continued development of new products based on this business.

According to the further disclosed roadmap on September 23, Cornelis's next-generation CN7000 plans to support interconnect standards like UALink, offering combinations of network cards and switching chips. Its role is to provide hardware and software for achieving interconnects; clients adopting open standards still need to purchase such products to connect accelerators.

Cornelis adds selling points to this product suite by having network equipment handle part of the data processing. For example, when multiple accelerators jointly train a model, results from each must be aggregated and redistributed; if network cards and switching chips can partially merge data during transit, it reduces repetitive sending, receiving, and processing at the accelerator end. The company also plans to support inference cache movement, reducing host communication overhead.

The company calls these functions Active Compute Fabric and plans to equip them with programmable processing cores, enabling new operations to be added via firmware updates. For clients, the value lies in reducing the time purchased accelerators wait for data. Specific benefits depend on tasks and system configurations; Cornelis's currently published utilization improvements mainly come from model calculations.

According to its latest timeline, the CN7000 aims to enter customer deployment in 2028 with this route fully realized. This generation of network cards plans to work on standard Ethernet networks and can add functions when paired with its own switching chips. Clients can thus first validate the network cards and assess whether to adopt more matching products after confirming benefits. Cornelis's previously accumulated customer relationships provide opportunities to access projects, but the new architecture must still complete its own introduction process.

Delos Data chose to enter through the interface connecting accelerators to networks. Its Data Interface, released on September 15, offers three forms: chiplets, near-package optical components, and boards, targeting accelerators as well as CPUs, memory, and other devices. It also needs to coordinate with clients' selected interconnect protocols and systems, focusing on orchestrating data exchange between different devices and handling some faults at the interface.

The three forms correspond to different collaboration stages. Chiplets require participation in the design and packaging of next-generation accelerators, while boards provide system-side access. Delos thus targets both chip design companies and clients building servers and clusters; its project entry depends on when clients finalize chip, packaging, and network schemes.

As the number of accelerators increases, a problem with one chip or link may leave other devices waiting for data. Delos hopes to have hardware interfaces detect faults and manage recovery, reducing impacts on the entire task. Currently, its cluster platform is used in existing infrastructure, with new server products planned to sample by the end of 2026.

In this release, Delos also added pre-deployment design and simulation tools to its cluster platform. Clients can utilize PCIe cards to validate real workloads, test interfaces through pre-tape-out simulations, and compare different connection methods and fault scenarios in cluster-level models. This allows chip design, network layout, and software tasks to be evaluated together in advance, enabling clients to identify adaptation issues in schemes before deciding to build.

Delos also disclosed over $100 million in financing on the same day, explicitly allocating funds to expand software and hardware engineering teams, product development, and sales. Validation tools are also part of its product offerings to clients. For such companies, R&D investment must cover software and system support beyond interface chips, while client introduction work continues through testing, deployment, and operational stages.

On September 21, Qualcomm, Lumentum, and Corning announced a joint demonstration plan for connecting optical chips via fiber, aiming to extend high-density connections up to tens of meters. In this scheme, Qualcomm provides the inter-chip interface subsystem, Lumentum provides the optical engine, and Corning provides the fiber connection, requiring joint design of the chip-side electrical interface and subsequent optical signal transmission. This combination targets future near-package and co-packaged optical systems and remains at the concept validation stage.

Buyers are also controlling combination complexity. Natalie Serrino, co-founder of inference infrastructure company Gimlet Labs, stated in an interview published on September 21 that the company aims to use two to four chip types in a data center and seek repeatable deployment combinations. Different chips can handle their be good at computations, but increasing chip varieties also raises connection and software adaptation work.

04 Conclusion

Whether Apple re-enters the commercial server market remains to be confirmed. The interconnect market is expanding, with suppliers' products at various stages. Next, whether products can pass client validation, operate stably with different chips, and deliver on schedule will affect these companies' progress in securing orders and expanding deployments.