With TSMC's 3-nanometer process gradually gaining recognition from chip companies, Intel recently pointed out that TSMC's 3-nanometer process is not really 3-nanometer, and is similar to Intel's 7-nanometer process, showing that Intel is indeed panicking as its chip process development lags behind.

Intel pointed out that its 7-nanometer process achieves a transistor density of 123.4 million transistors per square millimeter, while TSMC's 3-nanometer process achieves 124 million transistors per square millimeter. The number of transistors in both is similar, but the naming differs significantly.

This is not the first time Intel has accused TSMC. Since TSMC's mass production of 10-nanometer process, Intel has repeatedly accused TSMC of falsifying chip process specifications. This is mainly because after Intel mass-produced 14-nanometer in 2014, the mass production of 10-nanometer and 7-nanometer processes has been repeatedly delayed.

Apart from Intel, chip companies like Qualcomm have also questioned TSMC's advanced process specifications in the past. However, for chip manufacturers like TSMC and Qualcomm, more advanced processes are effective marketing strategies and indeed improve chip performance and reduce power consumption. Therefore, all parties have gradually accepted this naming convention.

Realizing that accusing TSMC of falsifying chip process specifications did not benefit Intel, in recent years, Intel has also begun to modify its chip process naming convention, renaming its 7-nanometer process as Intel 4 and the improved version of the 7-nanometer process as Intel 3. However, the transistor density of the Intel 3 process is higher than TSMC's 3-nanometer process.

The change in the naming convention of chip processes actually began after the 28-nanometer process. Before that, the gate spacing roughly corresponded to the process naming. For example, the gate spacing of 90-nanometer was below 90 nanometers, and the gate spacing of 65-nanometer was below 65 nanometers. However, after 28-nanometer, it became increasingly difficult to shorten the gate spacing in chip processes.

In the past, TSMC's research and development of 20-nanometer and 16-nanometer processes were not very successful. The performance of the first-generation 16-nanometer process was even inferior to 20-nanometer, leading most chip companies to abandon 16-nanometer. The first-generation 16-nanometer process only gained two customers. Subsequently, TSMC introduced 3D structure FinFET for the 16-nanometer process, which was a huge success. This also led to the reduction of gate spacing being significantly slower than that above 28-nanometer.

It can be said that after 16-nanometer FinFET, the naming convention of chip manufacturing processes has undergone a significant transformation. Since then, chip process naming has been based on equivalent processes, where if the chip performance can be improved by 20% to 30% or more, it is named as a new generation of process. By the time of 3-nanometer, the improvement speed of chip process performance has become slower. TSMC claims that the 3-nanometer process can improve performance by 10%-15%, and the A17 processor produced using this process only improved performance by 10%.

Even so, TSMC's 3-nanometer process also has the problem of a significant decline in yield. The yield of the first-generation 3-nanometer process is as low as 55%. Nowadays, TSMC is striving to improve the 3-nanometer process, hoping to increase the yield of the second-generation 3-nanometer process to over 90%. This result is due to the fact that as the gate spacing shortens, the electron breakdown effect becomes more severe. To ensure reliability and durability, memory chips have