The 2026 World Artificial Intelligence Conference (WAIC 2026) highlighted "hypernodes" as the undeniable centerpiece. According to preliminary data, over 20 companies unveiled hypernode-related solutions, with cutting-edge concepts such as 10,000-card clusters and terabit-level interconnect bandwidth emerging prominently. Hypernodes have firmly established themselves as the mainstream form of next-generation intelligent computing infrastructure.

The AI industry is experiencing a fundamental shift in direction. Over the past two years, the focus has transitioned from large-scale training to high-performance inference, further evolving into complex multi-Agent collaboration. The training phase prioritized 10,000-card clusters, large-scale synchronization, and high throughput. In contrast, the inference phase demands cost-effectiveness, low latency, and high efficiency.

The rise of inference has introduced new technical requirements. Firstly, PD (Prefill-Decode) separation has become standard, with Prefill clusters handling "comprehension" and Decode clusters managing "generation." This necessitates high-frequency, low-latency data transfers of KV Cache across layers and nodes. Secondly, the MoE (Mixture of Experts) architecture has transformed communication patterns from static All-Reduce in training to dynamic, fine-grained All-to-All and Token Dispatch. This requires capabilities like multi-plane communication, dynamic load balancing, and packet spraying—features unsupported by traditional static topologies. Thirdly, KV Cache expansion necessitates "storage-network" integration. As context lengths increase, KV Cache can occupy tens of GBs of memory, compelling systems to implement three-tier caching.

Building on inference paradigms, Agents elevate complexity to the system level. Agents are not single model calls but multi-step closed loops involving planning, tool invocation, retrieval, code execution, and result verification. Each step involves multiple inference calls, with decode stages generating KB-level KV Cache data communication. To saturate bandwidth exceeding 100GB, systems must initiate extremely high-frequency communications—a fine-grained, high-concurrency characteristic vastly different from the large-message synchronization and compute-intensive nature of traditional training.

Whether for inference or Agents, these underlying demands are disrupting traditional interconnect architectures and presenting new challenges to interconnect technologies at various levels. At the Scale Out level, networks are no longer static data pipelines. The rise of MoE architectures has shifted communication patterns from fixed to dynamic, requiring networks to support token-aware and expert-aware dynamic scheduling, along with advanced features like multi-plane, multicast, and packet spraying. Traditional InfiniBand (IB) protocols for supercomputing are costly and ecosystem-closed, while standard Ethernet lacks native optimization for AI workloads. At the Scale Up level, hypernodes require terabit-level bandwidth and nanosecond-level latency to support PD separation, MoE expert parallelization, and expanding KV Cache hierarchical storage. Capabilities like memory semantic access, synchronous Load/Store, and asynchronous RDMA become essential for hypernode chiplet interconnects. At the Scale Inside level, as compute die areas continue to expand (area scales quadratically with compute power, while perimeter and IO capacity scale linearly), IO density at chip edges has become a physical bottleneck. Traditional approaches of connecting compute chips directly via SerDes are hitting interconnect density ceilings.

Zhu Jundong, Co-founder, VP of Products & Solutions at Dimensional AI

In discussions, Zhu Jundong, Co-founder and VP of Products & Solutions at Dimensional AI, emphasized: "In the cloud era, the focus was on data management; during AI training, it was high-speed channels; now, with Agentic AI, deterministic transmission is paramount." This signifies that AI interconnect technologies must evolve from general-purpose network accessories to AI-native solutions.

02 IO Decoupling, AI NICs, and Optical Interconnects: Reconstructing the Technology Stack

Facing these challenges, the industry is shifting from compute-centric architectures to system-level co-design. Dimensional AI's Kiwi Fabric architecture addresses these challenges at the foundational level. It encompasses three dimensions: first, a unified interconnect architecture connecting compute and storage units across different locations and functions via open protocols; second, a complete product stack covering the full chain from Scale Inside to Scale Out; and third, the KANDA software orchestration platform for unified management of data and AI infrastructure.

Dimensional AI's Full-Stack Interconnect Products and Solutions

IO Die Decoupling: From "Monolithic Chips" to "LEGO-like Modularity"

The key to solving Scale Up bottlenecks lies in decoupling compute and IO. Dimensional AI anticipated this trend in 2021, pioneering domestic research on general-purpose hypernode chiplets. As compute dies grow larger, their area (scaling quadratically with compute power) outpaces perimeter growth (scaling linearly with IO capacity). Limited edge length gets consumed by memory and compute functions, severely compressing IO space. By chipletizing IO functions into a dedicated IO Die connected via UCIe protocols to compute dies, IO density can be dramatically increased. Die-to-Die interface physical density far exceeds traditional SerDes-based compute die connections. This architecture not only relieves area pressure on compute chips but also enables modular hardware design akin to LEGO blocks: compute dies, IO dies, and memory dies can iterate independently and combine flexibly for different scenarios, significantly reducing R&D cycles and costs. Future evolution will lead to Unified I/O Dies (KUIO), pooling CPU, GPU, XPU, memory, and even NIC chiplets through unified interfaces for true resource pooling and heterogeneous interconnects.

Dimensional AI's 800G AI Super NIC (SNIC) Platform

AI-Native NICs: Adapting to New AI Era Characteristics

At the Scale Out level, traditional NICs cannot meet AI inference's complex demands. Dimensional AI's Kiwi AI SNIC positions itself not as a simple network interface card but as the "high-speed communication processing core for AI data networks." For Agent scenarios with high-concurrency small messages, it supports ultra-high PPS (packets per second) and throughput efficiency. For MoE's dynamic communication, it enables multi-plane communication, efficient packet spraying, and rapid channel matching. For storage-compute convergence, it integrates PCIe Switch and high-performance RDMA for seamless GPU-storage connectivity. Critically, it employs an HPDE (Hybrid Programmable Data Engine) architecture—a middle ground between rigid ASICs and fully flexible software—delivering near-hardware performance on data paths while adapting through programming to rapidly evolving AI algorithm requirements.

Dimensional AI's Optical Interconnect Ecosystem Collaboration with Turin Quantum and Singularity Photonics

Optical Interconnects: Breaking Electrical Limits

As cluster scales expand and interconnect densities climb, electrical signals face increasing physical limitations in distance, power, and bandwidth. Optical interconnects are widely recognized as the direction for next-generation infrastructure, evolving from LPO (Linear Pluggable Optics) to NPO (Near-Package Optics), CPO (Co-Packaged Optics), and eventually OIO (Optical I/O). Dimensional AI collaborates with optical partners like Turin Quantum and Singularity Photonics on pre-research in AI chip-end optical interconnects. Industry projections suggest switch-side optical interconnects could see large-scale commercialization around 2027, with AI chip-end optical interconnects gradually deploying between 2028–2030. Dimensional AI is positioning itself early for this window.

03 Hypernode Era Demands Third-Party "Interconnect Solution Providers"

As the industry evolves, a stark reality emerges: not all AI chip companies are suited to build full-stack interconnect capabilities in-house. Zhu Jundong noted in interviews: "Compute and interconnect are distinct technical domains. NVIDIA's network advantage stems from nearly two decades of technology accumulation since acquiring Mellanox in 2019." For domestic GPU and NPU manufacturers, developing interconnects in-house requires massive time and capital investments and risks slowing primary chip iteration due to cross-domain technical gaps.

This is where third-party full-stack interconnect providers add value. Dimensional AI offers not single chips but full-stack solutions covering Scale Inside (UCIE IP), Scale Up (hypernode chiplets), Scale Out (AI Super NICs), and even Scale Across (cross-data center interconnects), along with the KANDA unified orchestration platform. This model enables domestic AI chip companies to rapidly acquire hypernode capabilities while focusing R&D resources on compute cores, avoiding solitary exploration in interconnects' "deep waters." More importantly, hypernode competition is not about single technologies but ecosystems and standards. During WAIC 2026, Dimensional AI jointly initiated the "Domestic Hypernode Ecosystem Co-construction Proposal" with core industry players including Biren Technology, Moore Threads, Iluvatar CoreX, Enflame Technology, SenseTime, Sugon, and ZTE. Previously, Dimensional AI actively participated in hypernode standardization, including OISA1.0, OISA2.0, and ETH-X protocols, aiming to break fragmentation and establish unified physical layer, link layer, and collective communication interface standards. In May, they partnered with China Mobile to release an OISA-based inter-card interconnect prototype verification platform, accelerating OISA standard industrialization and ensuring efficient interconnects among AI chip vendors under unified standards, laying a solid foundation for future domestic chip verification and adaptation.

Building an AI computing power ecosystem requires "promoting open collaboration, jointly constructing infrastructure layouts, and jointly expanding scenario applications." No single company can independently complete the entire chain from materials, packaging, chips to systems.

04 Conclusion: From "Giant Trees" to "Entire Forests"

The AI industry stands at a critical inflection point. As single-point computing power growth flattens, as Agent applications impose stricter system determinism requirements, and as hypernodes become standard for intelligent computing infrastructure, interconnect technologies have moved from behind the scenes to center stage, becoming the core variable defining cluster efficiency.

The hypernode frenzy cannot obscure a fundamental truth: no matter how powerful, compute chips without efficient, flexible, and open interconnect foundations remain isolated fragments of computing power. From IO Die decoupling to AI-native NIC evolution, from electrical to optical interconnect transitions, from closed ecosystems to open standard co-construction—these "infrastructure" efforts decisively shape China's AI computing power development. This requires ecosystem collaboration. As Dimensional AI founder Tian Mochen stated, "We must unite as one and advance together. We once pursued the height of single giant trees; today, we must connect all trees into a forest—roots intertwined underground, branches linked above. Internally, this forms a self-sustaining nutrient-sharing ecosystem; externally, it builds a strategic defense against risks. Only through system-level end-to-end collaboration and building a fully domestic closed-loop capability can we gain a firm foothold in global competition and ensure the industry's healthy growth."

【AI Evolution】Episode 5: Dimensional AI
Founded in 2021, Dimensional AI is an industry-leading provider of full-stack AI network interconnect products and solutions. Leveraging advanced high-performance RDMA and chiplet technologies, the company innovatively developed the unified interconnect architecture—Kiwi Fabric—tailored for hyperscale AI computing platforms to meet their stringent high-performance interconnect requirements. Currently, Dimensional AI offers key products addressing different interconnect tiers: AI-native Super NICs for northbound Scale-out networks, GPU inter-chip interconnect chiplets for southbound Scale-up networks, and UCIe Die2Die IP for on-chip compute expansion. Together, these products form a full-chain interconnect solution firmly supporting AI computing.