LightCounting, a market research firm in the optical communication industry, pointed out in its latest report that the optical communication chipset market is expected to grow at a compound annual growth rate (CAGR) of 17% between 2025 and 2030, with total sales increasing from approximately $3.5 billion in 2024 to over $11 billion in 2030.

Currently, optical chips are attracting increasing interest from research institutions and major companies.

01Market and Research Focus

Undoubtedly, Ethernet and DWDM are the two major drivers of market growth, occupying an absolute dominant position. Meanwhile, PAM4 DSP chips have quietly emerged as the third largest market segment. These chips are primarily used as onboard retimers between switch ASICs and pluggable ports. It may sound complex, but simply put, they are crucial for faster and more stable data transmission. According to LightCounting, the surge in demand for 400G/800G Ethernet optical modules, driven by investments in AI infrastructure by hyperscale cloud service providers, is boosting sales of PAM4 chipsets.

Massive investments in AI infrastructure by hyperscale cloud service providers are driving a surge in shipments of 400G/800G Ethernet optical modules.

Chinese cloud providers are beginning to follow suit and invest in AI infrastructure.

As an emerging market for PAM4 optical devices, wireless fronthaul is expected to recover in 2025 and continue to grow in 2026.

Since 2024, giants like NVIDIA and Intel have been increasing their investments in photonics technology. NVIDIA plans to launch the Rubin Ultra GPU compute engine in 2027, integrating co-packaged optics (CPO) technology to address data transmission bandwidth bottlenecks, and plans to collaborate with TSMC and Broadcom in 2025 to promote the mass production of related silicon photonics products. Intel, on the other hand, showcased its optical compute interconnect (OCI) chip at the Optical Fiber Communication Conference (OFC), enabling co-packaging with CPUs and providing a solution to meet the high bandwidth requirements of future AI computing. A month later, Lightmatter, a photonics acceleration computing startup, raised $400 million in Series D funding, valuing the company at $4.4 billion. This funding will be used to accelerate the production and deployment of the company's optical chips to meet the demand for low-energy, high-performance computing in AI clusters.

In addition, top research institutions both domestically and internationally have made advanced scientific achievements in the field of optical chips.

A team led by Professor Zou Weiwen from Shanghai Jiao Tong University has developed a new photonic tensor processing chip that enables high-speed tensor convolution operations. The research innovatively proposes an interdisciplinary research approach to constructing the tensor operation process based on photonic integration methods, which eliminates the need for tensor-to-matrix conversion and enables streaming computation from input tensors to output tensors. Based on this innovative approach, the team designed and developed a photonic tensor processing chip, which was validated on multi-channel images for high-speed tensor convolution operations at a clock frequency of 20 GHz, with a chip computing density of 588 GOPS/mm2. By increasing the scale of photonic device integration, the computing density is expected to reach over 1 TOPS/mm2 in the future. The research team utilized this chip to construct a convolutional neural network for video action recognition, with the convolutional layers in the network being completed on the photonic tensor processing chip, ultimately achieving a recognition accuracy of 97.9% on the KTH video dataset, close to the ideal recognition accuracy of 98.9%.

According to the School of Electronics and Electrical Engineering at Shanghai Jiao Tong University, this research finding demonstrates that photonic integrated chips can achieve tensor streaming processing at ultra-high clock frequencies, solving the problems of additional memory occupation and access, and providing a new technological approach for building advanced information systems such as high-performance computing and broadband signal processing.

A research team from Tsinghua University has developed a photonic chip named "TaiChi," which boasts energy efficiency several orders of magnitude higher than current smart chips. In just four months, Tsinghua University's optical chip has rapidly evolved to the second generation, the world's first all-optical AI chip, TaiChi-II, with energy efficiency surpassing that of NVIDIA's renowned H100. This is not only a technological breakthrough but may also signify the beginning of a new computing paradigm, potentially revolutionizing the design and construction of computers. This research was published in the August 7 issue of Nature. Reviewers at Nature believe that it has the potential to become a widely adopted tool for training optical neural networks and other optical computing systems.

Built on the newly developed full forward mode (FFM), the TaiChi-II all-optical AI chip allows for direct computation-intensive AI training in optical systems without the need for complex backpropagation processes, making it the world's first chip capable of "large-scale optical training," enabling faster and more energy-efficient training of AI models.

A team led by Associate Professor Wang Cheng from City University of Hong Kong, in collaboration with researchers from The Chinese University of Hong Kong, has developed a microwave photonic chip with faster processing speeds and lower energy consumption. It can perform ultrafast analog electronic signal processing and computation using optics. According to introductions, this chip is 1000 times faster and consumes less energy than traditional electronic processors, with a wide range of applications including 5/6G wireless communication systems, high-resolution radar systems, artificial intelligence, computer vision, and image and video processing.

In addition, IBM has made a breakthrough in photonic chips, realizing the next-generation high-speed optical interconnection technology, which can significantly improve the way data centers train and run generative AI models, increasing AI speed by 80 times. Compared to the current most advanced CPO technology, IBM's innovation allows chip manufacturers to add six times as many optical fibers to the edges of silicon photonics chips, known as "beachfront density." These fibers, with diameters approximately three times that of a human hair and lengths ranging from a few centimeters to several hundred meters, can transmit terabits of data per second. The IBM team assembled a high-density PWG on optical channels with a 50-micron pitch using standard assembly and packaging processes, with adiabatic coupling to silicon photonic waveguides. The paper also notes that these CPO modules with 50-micron pitch PWGs have passed all the stress tests required for manufacturing, including high-humidity environments, temperatures ranging from -40°C to 125°C, and mechanical durability tests, ensuring that the optical interconnection does not damage or lose data when bent. Furthermore, researchers have demonstrated PWG technology down to a pitch of 18 microns, with the stacking of four PWGs enabling connections for up to 128 channels.

This breakthrough continues IBM's leadership in semiconductor innovation, including the realization of the first 2nm node chip technology, 7nm and 5nm process technologies, nanosheet transistors, vertical transistors (VTFET), single-cell DRAM, and chemically amplified lithography. CPO technology provides a new solution to meet the growing performance demands of AI and is expected to replace electrical communication methods outside modules.

02Development Trends in Optical Communication: 1.6T, Silicon Photonics, LPO, CPO

The optical communication industry is accelerating towards higher speeds, integration, and lower power consumption, with the four major technological trends of 1.6T, silicon photonics, LPO, and CPO intertwining to drive industry transformation.

1.6T high-speed optical modules have become a core requirement for the next generation of data centers. By integrating 3nm DSP chips with silicon photonics technology, they achieve a single-wavelength transmission rate of 1.6Tbps, with a 40% reduction in power consumption compared to previous generations, supporting long-distance high-density interconnections for AI computing clusters. However, challenges remain in signal integrity design and heat dissipation. As a foundational innovation, silicon photonics technology leverages silicon-based materials and CMOS processes to integrate lasers, modulators, and other devices onto a single chip, significantly reducing costs and power consumption. It has become a key pillar for advanced packaging such as CPO, but the inefficiency of silicon-based lasers and packaging compatibility issues still limit its large-scale application.

LPO (Linearly Driven Pluggable Modules) focuses on "DSP removal," reducing power consumption by 50% and latency by 30% through linear direct drive technology while retaining pluggable features, achieving a balance of performance and cost in medium- and short-distance scenarios such as interconnecting top-of-rack switches in data centers. However, it is limited by transmission distance and the supporting capability of dedicated chips.

CPO (Co-Packaged Optics) is even more radical, co-packaging optical engines with switching chips to reduce energy efficiency to ≤5pJ/bit (a 70% reduction in power consumption), supporting future ultra-high rates of 3.2T/6.4T, and potentially increasing single-rack compute density by 40% when combined with liquid cooling. However, high integration brings challenges in heat dissipation, and the reliance on external light sources poses a bottleneck for commercialization.

In terms of synergistic effects, the deep integration of silicon photonics and CPO drives high-density integration, with LPO serving as a transitional solution to fill the medium- and short-distance market, and 1.6T driving bandwidth upgrades for long-distance applications, forming a multi-tiered technology coverage. At the industry level, leading companies are capturing the high ground of AI computing power through the combination of "silicon photonics + CPO," while LPO manufacturers are focusing on low-cost scenarios, pushing data center PUE from 1.25 to 1.12, and accelerating the implementation of green computing power. These trends collectively point to a core objective: in the era of AI and computing power explosion, to carry the exponential growth of data floods with lower energy consumption.

03Indium Phosphide: The Sweet Spot for Optical Chips?

Lastly, let's talk about the risks associated with optical chips. According to Yole statistics, global sales of indium phosphide substrates (converted to two inches) for optical module devices are expected to exceed 1 million units by 2026, with a compound annual growth rate of 13.94% from 2019 to 2026. The projected market size for indium phosphide substrates for optical module devices in 2026 will reach $157 million.

The core difficulties in the manufacturing process of indium phosphide (InP) optical chips focus on material properties, process precision, and thermal management.

Polycrystalline synthesis of indium phosphide requires precise control of the indium-to-phosphorus atomic ratio (1:1±0.0001) and temperature (within ±0.5°C) to avoid non-stoichiometric defects. The single-crystal growth process is susceptible to thermal field disturbances, resulting in dislocation densities exceeding 1000/cm, which directly affects the photoelectric conversion efficiency of the device.

Additionally, there are challenges in nanometer-scale epitaxy and grating manufacturing. The thickness of the quantum well epitaxial layer must be controlled within ±1nm, and fluctuations in the V/III group gas flow ratio must be <0.1% to ensure interface steepness. The etch depth tolerance for the second-order grating of distributed feedback (DFB) lasers must be ≤5nm; otherwise, wavelength shifts exceeding ±0.5nm will occur, making it difficult to meet dense wavelength division multiplexing (DWDM) requirements.

Furthermore, there are challenges in high-precision packaging and yield improvement. The alignment precision for optical fiber coupling is required to be <0.15μm, but welding stress can easily cause the VCSEL array spot to shift by more than 0.2μm, resulting in a packaging yield of less than 75% for 400G optical modules. Meanwhile, the facet reflectivity of EML lasers needs to be stabilized between 30%-40%, and coating thickness errors exceeding ±1nm can cause mode hopping.

In summary, the manufacturing process for indium phosphide is relatively complex and costly, limiting its large-scale application. To reduce costs and improve production efficiency, researchers are continuously optimizing the manufacturing process and exploring new preparation methods.