Huawei recently unveiled the foldable phone PuraX, capturing significant industry attention. A teardown video revealed that the chip extracted from this latest device is notably thicker, indicating a shift. The Kirin 9020 chip in the Huawei Pura X employs a novel integrated packaging process.

The teardown video demonstrates that the packaging approach for Kirin 9020 has transitioned from a sandwich structure to an integrated SoC and DRAM packaging format. It remains unclear whether this is CoWoS, InFO-PoP, or another form of packaging. Nonetheless, this marks another milestone in China's advanced packaging capabilities, signaling the initial stages of collaboration among domestic chip design, packaging, and memory factories.

Apple's mobile phone SoCs have previously utilized similar advanced packaging technology, vertically stacking DRAM on top of the SoC, known as TSMC's PoP. However, the SoC itself remains a singular integrated chip.

When Apple's iPhone debuted in 2007, it was swiftly disassembled and publicly showcased, introducing layered packaging technology to the masses. PoP was once a focal point but then disappeared for a considerable period. Later, more advanced phones combined processors and memory, making PoP a packaging option once again.

Package on Package (PoP) is an integrated circuit packaging technology that encapsulates two or more chips into a single unit. Commonly used in mobile devices and other small electronics, this technology conserves space and enhances performance. In PoP, chips are layered, with one placed atop another, connected through soldering or other techniques. Typically, the upper chip is a processor or memory, while the lower chip is DRAM or another memory type.

InFO (Integrated Fan-Out) technology, introduced by TSMC in 2016, represents another packaging advancement. InFO-PoP refers to the configuration of InFO packaging for PoP. InFO places chips directly on the substrate and connects them through RDL (Re-distributed Layer), eliminating wire bonding. RDL, formed on the wafer surface, enables larger bonding pad spacings, supporting more I/O connections for a more compact and efficient design.

Wafer-level packaging often necessitates RDL technology due to the prevalence of aluminum pads on wafers. Whether at the wafer or board level, aluminum metal is challenging to process, necessitating another metal to cover it. RDL alters the contact position of originally designed chip circuit connection points (I/O pad) through wafer-level metal wiring and bump processes, adhering to the minimum solder ball spacing constraint.

InFO technology was first applied to Apple's A10 chip in 2016, spawning new applications: InFO-oS, InFO-LSI, InFO-PoP, and InFO-AiP.

InFO-oS technology integrates multiple advanced logic chips, achieving higher package integration, suitable for 5G networking. InFO-LSI technology, akin to Intel's EMIB, optimizes interconnect bandwidth and cost, enabling high-speed signal transmission within a package, thus boosting system performance and power efficiency. Ideal for high-performance computing, AI, communications, and networking, InFO-LSI addresses complex intra-package data processing and communication needs. InFO-PoP combines InFO with PoP, common in applications requiring multiple chip integration, like mobile devices, offering higher integration and functionality. InFO-AiP integrates antennas into InFO packages, facilitating compact design and superior signal transmission. Typically used in mobile devices, IoT, and communication equipment, InFO-AiP ensures exceptional wireless connectivity.

The iPhone 7's A10 processor, launched in 2016, utilized TSMC's 16nm FinFET process and InFO technology, successfully integrating AP and LPDDR into a single package, setting a new standard for mobile packaging. InFO packaging became crucial for TSMC to secure Apple's A-series processor orders. That year, TSMC was the sole producer of InFO packaging. Over time, Apple's A-series processors and DRAM have been packaged together using TSMC's InFO-PoP technology, leveraging Through InFO Via (TIV) to connect DRAM bumps to the RDL layer and interconnect with the logic chip, reducing chip size and board area while ensuring robust thermal and electrical performance.

What advantages does this technology offer?

Flexibility is a key advantage, as DRAM packages can be easily replaced. Additionally, PoP technology conserves space by stacking chips, making devices smaller and lighter. Shorter chip connections enhance performance and reduce latency.

With InFO's RDL layer, chip designers can reduce costs by replacing part of the internal circuit design with RDL design. RDL supports more pin counts, allows flexible I/O contact spacing and larger bump areas, reducing stress between the substrate and components, thus improving reliability. Made of polymer-based thin-film material, the RDL layer can replace the packaging carrier board, saving costs and enabling multi-chip package interconnection.

Apple has been an early adopter of advanced packaging for mobile chips, driven by several factors:

Apple collaborates closely with TSMC on advanced packaging, often among the first high-net-worth customers to adopt cutting-edge manufacturing processes. Given the escalating costs of advanced nodes, Apple has a pressing need to adopt cost-effective packaging solutions. For instance, 3nm tape-outs and wafers cost double that of 5nm, and 2nm costs will double again, unaffordable even for high-net-worth customers.

Apple's M1 Ultra chip, enabling high-speed internal GPU communication, showcases its efficient D2D communication protocol and physical layer design, ahead of the ARM camp. Applying this to future mobile SoCs will be easier for Apple. This requires advanced packaging support, and Apple has innovatively customized the UltraFusion packaging architecture.

Moreover, Apple has a strong demand for IP reuse. Its chips span mobile phones, tablets, laptops, and workstations, with IPs like baseband and Wi-Fi controllers sourced from Qualcomm and Broadcom. With Apple's self-developed baseband, these modules may gradually transition to in-house solutions, necessitating reusable and replaceable SoC modules for cost-effectiveness. Here, the Chiplet packaging process excels.

Currently, the Android ecosystem is also embracing this trend, driven by foundry costs and IP reuse demands for PC chips, necessitating advanced packaging support.

Domestic mobile chip manufacturers are deeply collaborating with downstream partners to develop related technologies. A renowned domestic mobile SoC design company has disclosed a patent for chip stack packaging and terminal equipment (CN114287057A), addressing high costs associated with through-silicon via technology while ensuring power supply requirements, favoring cost reduction in advanced packaging.

Additionally, the HarmonyOS PC to be launched this May has a strong IP reuse demand. Qualcomm is also planning to enter the AIPC market, having previously launched the Snapdragon X Elite.

However, rumors suggest that starting from 2026, Apple will abandon the existing PoP design for memory in the iPhone 18 series, adopting a separate architecture for chips and memory.

Apple's hardware design philosophy is often described as "exquisite and minimalist." Its devices, including iPhones, iPads, and Macs, predominantly use PoP technology for chips and memory. While beneficial for space-constrained mobile devices by reducing chip area and shortening the physical distance between memory and the main chip, thus minimizing data transmission latency and improving power efficiency, PoP technology has limitations. The memory package size is constrained by the SoC, affecting I/O pin count and limiting data transfer rates and performance, particularly evident in high-bandwidth AI computing demands.

Apple's rumored plan to adopt a separate chips and memory design for the iPhone 18 represents a performance compromise. Physically separating memory from the chip increases the transmission path but unlocks more I/O pins, significantly enhancing data transfer rates and bandwidth.

Apple is reportedly collaborating with Samsung to develop next-generation LPDDR6 memory technology, expected to offer data transfer speeds and bandwidth 2 to 3 times higher than current LPDDR5X. This substantial performance boost is invaluable for smartphones increasingly reliant on local AI computing, supporting faster data throughput in AI real-time translation, image recognition, and a more intelligent Siri.

Furthermore, the separate design aids in thermal optimization. Physically separating memory from the SoC improves thermal efficiency, reducing performance bottlenecks caused by overheating chips.