Foreword:

On September 30, 2026, Synopsys, the world's largest EDA tool vendor, and OpenAI signed a multi-year cooperation agreement, designating each other as 'preferred partners' to jointly develop a dedicated model named GPT-Synopsys. The goal is to automate the chip design process and significantly shorten development cycles.

On the day of the announcement, Synopsys' stock price surged by over 10%, reaching $479. Synopsys holds over 50% of the global EDA market share, with revenues of approximately $5.7 billion in fiscal year 2025. OpenAI's valuation far exceeds $100 billion. These two top players in their respective fields have come together, aiming for a fundamental restructuring of the chip design process.

Author | Fang Wensan

Image Source | Internet

Chip Design Speed Becomes a Bottleneck for AI Industry Acceleration

As demand for AI model training and inference deployment surges across various sectors, the pace of chip iteration toward higher performance has accelerated significantly. However, over the past few decades, chip design has followed a somewhat unhealthy growth curve: whenever chip complexity doubles, design time nearly doubles as well. The traditional approach has been to increase the number of engineers to manage this pressure, but marginal costs are rising, and training a senior chip designer often takes years.

Chip design is not just about 'writing code.' It is highly complex, involving multiple stages from circuit description, logic synthesis, placement and routing, to physical verification. Engineers must repeatedly balance performance, power consumption, area, and cost. The cycle from concept to tape-out for a new chip typically spans years. During this period, market demands and AI algorithms may have already iterated several times. No matter how powerful NVIDIA's GPUs are, if the next-generation chip takes three years to arrive, the supply of computing power can only wait.

What Exactly Does GPT-Synopsys Do?

The core significance of this collaboration lies in AI's further penetration from general-purpose large models into the upstream EDA (Electronic Design Automation) sector of the semiconductor supply chain.

Currently, the industry's approach is to connect general-purpose large models to EDA tools—where models generate scripts, interpret errors, and assist engineers in operations. GPT-Synopsys is different. OpenAI co-founder Greg Brockman stated in the announcement video that OpenAI's model will learn how to use Synopsys' software tools, helping engineers handle various trade-offs and optimizations during the chip design process, 'thereby shortening the design process by weeks or months and bringing more chips to the world.'

To draw an analogy, existing AI-assisted EDA is like pairing an engineer with a theoretically knowledgeable intern. The intern can help with research and documentation, but operating the machine tools still falls to the engineer. GPT-Synopsys aims to let the intern directly operate the machine tools—not only capable of operation but also able to check whether the machined parts meet tolerances, adjusting parameters and reprocessing if necessary until the parts pass inspection before handing them over to the master for approval.

The specific workflow is as follows: Engineers set design goals—such as controlling power consumption within a certain range, converging timing to a specific node, and completing verification convergence—then hand the task over to an AI agent. The agent automatically invokes Synopsys' EDA tools, reads and analyzes output data, implements design modifications, and iterates repeatedly, ultimately submitting the verified results to the engineer for review.

If the AI model can learn and invoke Synopsys tools to automatically complete certain optimizations and trade-offs, it could theoretically significantly shorten design cycles, reduce trial-and-error costs, and free engineers from the manual labor of 'operating tools and Trial and error (repeated trial-and-error),' allowing them to focus on architectural decisions and directional judgments.

Why Synopsys for Accelerated Chip Iteration?

The growth logic of the EDA industry is changing. The iteration pace of chip R&D is rapidly accelerating. Ravi Subramanian, Synopsys' Chief Product Management Officer, stated in an interview, 'A complete chip design process must be compressed to within a year, while the number of chip projects in design is also increasing daily.' Traditional EDA tools are functionally comprehensive, but 'comprehensive' and 'fast enough' are two different things. If Synopsys does not proactively embed AI deeply into its own toolchain, general-purpose model vendors or cloud providers might bypass it and directly cut into (cut in from the upper layers) into the chip design entry point. Therefore, Synopsys has chosen to proactively integrate AI into its deepest moat—the tools themselves.

Now, looking at OpenAI. Greg Brockman made a straightforward remark in the announcement: 'By helping them build better chips, we can build better AI.' This statement reveals a harsh reality: The continuous improvement of AI capabilities is constrained by the iteration speed of underlying hardware. Earlier this year, OpenAI launched its self-developed inference chip, Jalapeo, which took nine months from design to tape-out. During this period, OpenAI's models were used to accelerate parts of the design and optimization processes. After tasting the benefits of using AI to accelerate chip design, OpenAI clearly wants to systematize and productize this capability.

Business Model Innovation: Pay-for-Performance

This collaboration between Synopsys and OpenAI is not a simple software licensing deal but a combination of 'training subscription fees + revenue sharing.' OpenAI first pays fees to learn how to use Synopsys' tools; when Synopsys' customers use GPT-Synopsys, the two parties then share revenue based on the model's degree of improvement in chip design. This pay-for-performance model helps alleviate customer concerns about the uncertain value of AI tools and aligns OpenAI's interests with the actual benefits received by Synopsys' customers.

This 'pay-for-performance' model is entirely different from traditional EDA's per-seat or per-tool licensing fees. Sassine Ghazi explained, 'We designed this agreement so that it does not cannibalize our own business. Since we are creating more value for our customers, this will be incremental to our business.' However, the two parties did not disclose key details such as the revenue-sharing ratio, exclusivity arrangements, or how customer design data would be used—these will be focal points of market attention in the future.

In terms of data security, Synopsys particularly emphasizes that customer-specific design data will not be used for training models. Data is encrypted during both static storage and transmission, and customers can manage their data through configurable data retention, auditing, and permission controls. This is crucial for the semiconductor industry—if a company's chip design files are leaked, the losses could amount to hundreds of millions of dollars in sunk costs.

Conclusion

This collaboration between Synopsys and OpenAI may not immediately solve all the pain points in chip design, but the direction is clear: The competition in chip design is shifting toward 'whose AI agent can iterate better.' When AI can operate tools, evaluate results, and optimize designs on its own, the rules of the chip design game may truly change.

Online References:

EE Times China: 'Synopsys Seeks Collaboration with Chinese AI Labs to Accelerate Chip Design in China'

Wall Street See: 'Synopsys and OpenAI Reach Multi-Year Framework Collaboration on Chip Design Models'

Smartkarma: 'Synopsys (SNPS.US) Partners with OpenAI to Develop AI Model for Chip Design, Revenue-Sharing Model Drives Stock Price Up 7%'