Foreword:

Today, DeepSeek and Zhipu have been thrust into the spotlight of "chipmaking," with whispers growing louder about a battle for control over costs, supply, and technology timelines.

Author | Fang Wensan

Image Source | Internet

Inference Chips as the Gateway

Recently, Reuters, citing anonymous sources, reported that DeepSeek is developing its own chips for AI inference, with the project launching about a year ago and still in its early stages.

The report noted that the company has engaged with chip designers, foundries, and memory firms, while recruiting chip design engineers through private channels.

Training is like building a reservoir: concentrated investment, clear project timelines, and frequent changes in model architecture demand extreme requirements for versatility, precision formats, cluster interconnection, and software flexibility.

Inference resembles urban water supply: once a model is deployed, every conversation, search, code completion, image generation, and agent call continuously consumes computing resources.

As user bases expand, first-token latency, tokens-per-second output, concurrency, cost-per-token, and performance-per-watt directly impact product gross margins.

China's intelligent computing cloud growth has etched pressure into market data. IDC revealed that China's AI IaaS market reached RMB 28.8 billion in H2 2025, up 132.1% YoY; the full-year figure stood at RMB 48.67 billion.

Zhipu's financials hit closer to home: the company reported RMB 724.3 million in revenue for 2025, up 131.9% YoY; cloud deployment revenue hit RMB 190 million, up 292.6% YoY, with cloud deployment gross margins rising from 3.3% in 2024 to 18.9%.

Business scaling and economies of scale are improving margins, yet R&D investment of RMB 3.18 billion and an adjusted net loss of RMB 3.182 billion remind the market: while model capabilities steal the spotlight, computing costs linger in the finance office.

This is where inference chips shine. Stable large-model workloads allow unused capabilities in general-purpose GPUs to be stripped away, focusing transistors, on-chip memory, memory bandwidth, and interconnection resources on common operators, low-precision computing, KV Cache, and MoE expert scheduling.

Custom chips need not win every benchmark test; they simply need to maximize "tokens-per-yuan" within their own models, traffic, and data centers to make the numbers work.

Google deployed its first-generation TPU for internal use in 2015; AWS claimed its first-generation Inferentia instances delivered up to 2.3x throughput and up to 70% lower inference costs versus comparable EC2 instances; Meta also stated its MTIA for ranking and recommendation inference workloads has been deployed at data center scale.

While vendor claims cannot be directly compared, they collectively illustrate a simple truth: only firms with massive, stable, and predictable workloads can wield chips as cost levers.

Vying for the "Algorithm-Hardware" Closed Loop + Cost Curve

DeepSeek's rationale lies in its existing engineering path. DeepSeek-V3 adopts a 671-billion-parameter MoE architecture, activating 37 billion parameters per token; through MLA, FP8 training, and communication optimizations, full training consumed 2.788 million H800 GPU hours.

This figure covers only the formal training process for this version, excluding prior research, experimentation, data processing, and infrastructure investment, yet it underscores a clear orientation: rather than simply stacking more chips, it focuses on aligning model architecture, numerical precision, operators, and cluster communication.

This makes DeepSeek ideal for custom inference chips, as it holds the most detailed workload profiles internally: which operators appear most frequently, how expert routing moves data, how KV Cache consumes VRAM, precision losses from low-precision formats, and communication bottlenecks.

Chip vendors face a market; model vendors face their own daily computations, repeated billions of times. The latter can adapt model structures to hardware or use hardware design to shape next-generation models.

DeepSeek-V3.1 publicly adopted the UE8M0 FP8 scaling format, while the DeepGEMM project continuously optimizes FP8, FP4, BF16, and MoE-related compute kernels.

These moves do not prove self-developed chips but show the team's deep hardware-aware optimizations. If the rumored inference chips advance, the true value may lie not in a TOPS figure but in the closed loop of model, compiler, operator library, and silicon co-evolution.

Zhipu faces a slightly different challenge: as a publicly traded company, faster API and cloud deployment growth intensifies market scrutiny over margins, capital expenditures, and computing supply.

GLM-5 has completed deep inference adaptation and operator-level optimization for domestic platforms like Ascend, Moore Threads, Cambrian, Kunlunxin, MetaX, and Enflame; GLM-5.2 expanded this to more domestic computing platforms.

For Zhipu, short-term gains may come from "one model, multiple chips" and procurement negotiation, with custom chips handling stable large-scale inference workloads only in the medium to long term.

While both firms appear to converge on the same path, their starting points differ. DeepSeek resembles pushing extreme engineering efficiency deeper into silicon; Zhipu resembles seeking long-term anchors for cost and supply after commercial scaling.

Securing Autonomous Computing Insurance

Tightening export controls have cast uncertainty over computing supply chains as a dark cloud over all domestic AI firms.

Zhipu, on the Entity List, can no longer procure NVIDIA's high-end GPUs and must wait in line for Huawei Ascend's limited supply, with computing gaps directly restricting business expansion—its official Coding packages remain perpetually oversubscribed.

While DeepSeek faces no immediate restrictions, supply chain policy volatility remains uncontrollable, and the risk of single-supplier dependency could explode at any moment.

According to an IDC report released in April 2026, China's total cloud AI accelerator shipments reached 4 million units in 2025, with domestic vendors delivering 1.65 million units, capturing 41% market share, while NVIDIA's share fell from over 90% at its peak to 55%.

Behind these impressive figures, training scenario localization remains below 15%, and the high-end computing bottleneck remains unresolved.

Both firms' chipmaking ventures aim not to disrupt the market overnight but to build backup channels for their computing supply, keeping survival and development baselines in their own hands.

Combined with the RMB 344 billion injection from the third phase of the National Integrated Circuit Industry Investment Fund and the localization bias in smart computing center procurements across regions, the industrial soil for cross-border chipmaking is gradually maturing.

"Having Our Own Chips" ≠ Computing Autonomy

The term "self-developed" easily creates a romantic illusion, as if drawing a blueprint automatically aligns the supply chain. Reality is far more complex.

For an AI chip to enter data centers, seamless coordination is required across architecture design, IP, EDA, verification, tape-out, wafer fabrication, advanced packaging, high-bandwidth memory, boards, servers, cluster interconnection, drivers, compilers, operator libraries, and inference frameworks. Any bottleneck renders paper computing power into expensive wall art.

Model firms rarely handle all links themselves; a more feasible path is mastering architecture definition and software-hardware collaboration (co-optimization), leaving specialized design services, IP, manufacturing, and packaging partners to handle their respective segments.

Here, "autonomy" should mean stronger selection rights, substitution capabilities, and iteration control—not completing the entire supply chain behind closed doors.

Custom chips also carry hidden costs: models evolve too rapidly. Architectures tailored for MoE, low precision, and long contexts today may clash with new attention mechanisms, sparsity patterns, or agent workloads two years later.

General-purpose GPUs are expensive but accommodate change; ASICs offer efficiency but risk being constrained by rigid designs. Model firms must simultaneously bet on technology routes, traffic scales, and production rhythms—a challenge akin to laying tracks on a moving train.

Conclusion:

For large model firms, discussing requirements and conducting feasibility assessments with chip design companies now holds strategic significance.

Only when prototype chips work, software stacks mature, servers deploy, and stable workloads emerge can they truly hold a usable computing foundation.

The chip industry ignores trending topics, and silicon does not respond to slogans.

Partial references: 36Kr: "DeepSeek, Zhipu Reportedly Building Chips as Domestic Large Models Bypass NVIDIA," Economic Observer: "Can Large Models Avoid the Chipmaking Path?," InfoQ: "DeepSeek Reportedly Developing Self-Built AI Inference Chips, Launched One Year Ago, Now Engaging Foundries and Memory Vendors," OFweek: "Zhipu to Develop AI Chips—Why Are Large Model Firms All Diving In?"