In the promotional materials for autonomous driving chips, TOPS (Tera Operations Per Second) has emerged as a near-standard metric. Chip specifications range from tens to hundreds, or even over a thousand TOPS, showcasing significant numerical differences among various options.

However, in actual mass-produced vehicles, chips with higher computing power do not necessarily translate to superior system performance.

This discrepancy arises because TOPS merely quantifies the number of operations a chip can perform under specific conditions.

Autonomous driving demands a comprehensive hardware and software system capable of delivering useful computational results in real-world scenarios, considering real data, models, and time constraints.

Consequently, by 2026, relying solely on TOPS comparisons will increasingly fall short in accurately assessing the true capabilities of autonomous driving chips.

What truly matters is the extent to which nominal computing power can be effectively harnessed.

01 Why TOPS Alone Isn't Enough

TOPS represents a chip's theoretical integer computing capacity.

For instance, a chip rated at 1000 TOPS can theoretically perform around one trillion operations per second under specified precision and computational methods.

However, this figure is based on theoretical conditions.

Manufacturers vary in their TOPS calculation standards. Some use INT8 calculations, while others provide data for INT4, INT8, and even FP16 simultaneously.

Moreover, some figures represent the peak sum of AI acceleration units across the entire SoC, while others combine the capabilities of different computational engines. Thus, a direct comparison of 1000 TOPS and 500 TOPS does not necessarily imply a twofold performance difference.

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Beyond statistical standards, Batch Size is another critical yet often overlooked variable. In AI inference, Batch Size refers to the number of samples processed by the chip in a single model pass.

To achieve impressive TOPS figures in laboratories, manufacturers typically set a large Batch Size (e.g., 128 or 256) to maximize AI computing unit utilization. However, autonomous driving requires low-latency real-time systems, necessitating a Batch Size of 1 (single-frame, single-pass inference) to minimize perception lag.

With Batch=1, significant computing power may remain idle during data loading, resulting in actual effective throughput often being only 20%–40% of the nominal peak. Comparing TOPS without considering Batch Size is akin to substituting laboratory data for real-world production concepts.

Neural networks do not always maintain AI computing units at 100% utilization during operation. Data transfer, memory bandwidth, cache hit rates, operator support, CPU-NPU scheduling, and data conversion between modules can all become bottlenecks.

In essence, a chip may boast a theoretical peak of 1000 TOPS, but the computing power continuously utilized by the autonomous driving algorithm may only be a fraction of that.

02 Understanding the Gap Between Nominal and Effective Computing Power

Effective computing power is a concept closer to real-world engineering outcomes.

Before delving deeper, a common misconception must be addressed.

During the compilation of this article, the editor encountered a formula: "Effective computing power ≈ Nominal computing power × Computational utilization × Precision and model matching efficiency × Memory and data transfer efficiency × Software stack efficiency."

However, such a simplistic multiplicative formula does not accurately reflect engineering realities, as these factors are highly interdependent.

Insufficient memory bandwidth directly leads to idle computing units (reduced utilization), and operator fusion optimization in the software stack primarily reduces transfer times rather than simply enhancing an isolated metric.

Therefore, effective computing power serves as a qualitative analytical framework rather than a quantifiable formula.

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The gap between nominal and effective computing power manifests in three main areas: utilization, model matching, and memory bandwidth.

Utilization: If an NPU peaks at 1000 TOPS but only averages 50% utilization during actual model operation, it is challenging to consider it a 1000 TOPS chip in terms of actual computational throughput.

Model matching: Different AI accelerators vary in their support for Transformers, CNNs, BEVs, Occupancy models, temporal models, and custom operators. A chip may have high theoretical computing power, but if many model operators cannot be efficiently executed on dedicated AI units and must be processed by the chip's built-in GPU or DSP, the peak computing power is difficult to fully leverage.

Memory bandwidth: Even with optimal utilization and model matching, insufficient memory bandwidth can bottleneck the transfer of model weights and intermediate feature maps. AI computing units will still await data, preventing the realization of peak computing power.

These factors ultimately impact end-to-end measured results, explaining why different chips may exhibit significant differences in FPS, latency, and power consumption for the same end-to-end model.

To measure effective computing power, one must examine the chip's end-to-end throughput and latency performance on real models.

03 Key Considerations for Autonomous Driving Chips

For autonomous driving, the critical factor is not the number of multiply-accumulate operations per second but whether the chip can stably complete perception, prediction, planning, and other tasks within a specified timeframe.

For example, if one chip achieves 30Hz and another only 15Hz when running the same end-to-end model, significant differences in actual system performance may exist, even if the TOPS difference is not substantial.

Autonomous driving is a real-time system where camera inputs, LiDAR point clouds, millimeter-wave radar data, and vehicle status information continuously enter the system.

The algorithm must complete data preprocessing, feature extraction, fusion, inference, and output within a limited time.

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Thus, the truly important indicators for autonomous driving chips are whether computing power, bandwidth, latency, and power consumption can simultaneously meet requirements in a Batch Size=1 scenario.

Especially as model sizes expand with Transformers and temporal modeling, computational and memory access pressures increase. Relying solely on TOPS becomes even more unreliable. Even with higher peak computing power, a chip may underutilize its NPU if memory bandwidth is insufficient or on-chip cache design is unreasonable.

04 Beyond the Chip: The Role of Software

By 2026, evaluating autonomous driving chips independently of the software stack will become increasingly challenging.

Compilers, operator libraries, model optimization toolchains, quantization schemes, memory scheduling mechanisms, and runtime systems will all directly influence final performance.

The same model may exhibit vastly different execution efficiencies on different chips. For example, after structural pruning, operator fusion, and INT8 quantization, a model's theoretical computational load may decrease. However, if the chip lacks hardware support for these optimizations, final latency may not decrease accordingly.

Conversely, a chip with mature compiler and operator optimization capabilities may achieve better actual performance through higher computational utilization, even if its nominal TOPS is not the highest in the industry.

Therefore, evaluating an autonomous driving chip now essentially means assessing the overall efficiency of the hardware-software-model combination.

05 The Importance of Power Efficiency

Another often-overlooked aspect of autonomous driving chips is power consumption.

While AI chips on desktop servers can rely on higher power consumption for performance, automotive chips must consider the vehicle's overall energy consumption, heat dissipation, and long-term stable operation.

Thus, simply comparing peak TOPS is becoming increasingly meaningless. What matters more is the effective computing power per watt.

For example, a chip with high peak computing power but significant power requirements to reach that peak may be less valuable for mass-produced vehicles than a chip with slightly lower peak computing power but lower power consumption for running the same model continuously.

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Especially as high-level intelligent driving systems evolve towards larger models, longer temporal sequences, and more complex multimodal inputs, computing power demands continue to rise, but power consumption cannot increase indefinitely.

Therefore, the core of future chip competition is likely not who has the highest TOPS but who can convert more TOPS into truly useful model inference capabilities at lower power consumption.

06 How to Compare Autonomous Driving Chips

By 2026, when comparing two autonomous driving chips, one should consider multiple dimensions beyond just TOPS.

Theoretical computing power under unified precision: Clearly specify whether it is INT4, INT8, or FP16, avoid direct comparisons under different statistical standards, and inquire whether the figure is a benchmark score under extremely large Batch Sizes or a single-Batch actual test closer to mass production.

Actual model throughput and latency: Include real test results for typical perception models, BEVs, Occupancy models, end-to-end models, and temporal models, and must account for the time consumption of pre-processing and post-processing (Pre/Post-processing), which often constitutes a larger proportion than inference itself.

Memory bandwidth, on-chip cache, AI computing unit utilization, and data transfer efficiency between the CPU, GPU, and NPU.

Software ecosystem: Include compilers, operator coverage, quantization toolchains, model migration costs, and stability and power consumption performance after mass production.

Only through such a comprehensive comparison can one approach the true computational capabilities that the chip can provide to the autonomous driving system.

07 Concluding Remarks

The future competition for autonomous driving chips is likely to shift from stacking TOPS to maximizing their utilization.

Nominal computing power indicates theoretical capacity, while effective computing power reflects actual system accomplishments.

The gap between the two precisely determines the true engineering value of an autonomous driving chip.

Therefore, the next time you encounter a chip claiming hundreds or even thousands of TOPS, the question should not be whether the number is high enough. Instead, ask:

What model does it run?

What is the actual utilization rate?

What latency is achieved at what power consumption?

These questions are often closer to the true capabilities of an autonomous driving chip than TOPS itself.

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