Competition among integrated chips is intensifying.

Internationally, according to a Semiengineering article, Intel Foundry, TSMC, and Samsung Foundry are all vying to provide all the fundamental components for full 3D ICs. Over the next few years, these components will work together to achieve performance improvements by orders of magnitude with minimal power consumption.

In terms of market data, a September report by Future Market Insights stated that the 3D IC and 2.5D IC packaging markets are expected to grow at a compound annual growth rate (CAGR) of 9.0%, reaching $58.3 billion by 2025 and $138 billion by 2035. Composite absolute growth analysis indicates that over the decade, the market will expand by nearly $79.7 billion, driven by increasing demand for high-performance computing, AI accelerators, and next-generation memory stacking.

Notably, the report highlights China leading the global market with a 12.2% growth rate, followed by India (11.3%), Germany (10.4%), France (9.5%), the UK (8.6%), and the US (7.7%).

In fact, China not only has market advantages but is also actively positioning itself in integrated chip technology and ecosystems. In the next semiconductor cycle, integration could replace manufacturing as the most critical link in the industry chain.

This is a race that cannot be lost.

01 Integrated Chips: Bypassing Moore's Law

As semiconductor manufacturing processes approach physical limits, the performance gains and cost-effectiveness promised by Moore's Law are significantly slowing down. Against this backdrop, chip integration technology, particularly heterogeneous integration centered around chiplets, is emerging as a key driver for industry development.

The core of this new direction in chip integration lies in its modularity and heterogeneity. Advanced packaging technologies enable the combination of chiplets from different process nodes, manufacturers, and even materials within a single package. For example, high-performance computing cores can be manufactured using the most advanced processes, while cost-sensitive I/O or analog modules can utilize mature process nodes. This approach not only optimizes the cost and performance of each functional module but also significantly shortens product development cycles and time-to-market by reusing existing chiplet designs.

The main advantages of integrated chips are reflected in three dimensions: performance, power consumption, and cost. At the performance level, technologies like 3D stacking vertically integrate memory and logic computing units, greatly shortening data transmission paths and effectively alleviating the "memory wall" bottleneck in traditional computing architectures, thereby improving data processing efficiency and bandwidth. This directly translates into lower power consumption, as data movement within the chip is one of the primary sources of energy consumption.

In terms of cost, the overall yield of manufacturing multiple small-sized chiplets is much higher than that of a single large-sized chip, reducing the risk of entire chip scrap (scrapping) due to a single defect and thus controlling manufacturing costs.

To support this technological direction, advanced packaging processes such as 2.5D and 3D packaging play a crucial role. These technologies achieve high-density interconnections between chiplets through methods like silicon interposers or through-silicon vias (TSVs). Currently, interconnection density has become a performance metric as important as transistor density. This high-density integration enables components within the package to achieve bandwidth several orders of magnitude higher than traditional PCB boards while consuming less power, providing the necessary physical foundation for data-intensive applications like high-performance computing and AI.

At the same time, 3D integrated chips are not just a competition of process nodes. They also involve significant changes in EDA tools and methodologies, digital twins, multi-physics simulations, advanced equipment support, and the infusion of AI across multiple stages of the design-to-manufacturing process. In a sense, these areas are even more critical in integrated chips.

02 EDA Platforms: The Soul of 3D Integration Design

3D packaging first requires the support of more advanced EDA tools.

The three-dimensional stacking architecture imposes new technical requirements on EDA tools. Design complexity has surged, shifting from two-dimensional layouts in a single process to system-level engineering involving multiple chips and various physical fields. Factors such as thermal management, mechanical stress, cross-chip timing convergence, and power integrity, previously secondary design considerations, have now become primary factors affecting system feasibility. Traditional EDA tools designed for planar chips struggle to handle this system-level complexity.

Therefore, the role of EDA software has evolved from a single-chip design tool to a platform supporting system-level integration. In response, the top three international EDA vendors—Synopsys, Cadence, and Siemens EDA—have all made deep layout (positioning) and launched a series of targeted solutions.

Synopsys' core product is the 3DIC Compiler platform, which integrates architecture exploration, implementation, analysis, and sign-off stages into a single environment based on a unified data model. Through its Synopsys.ai technology, particularly 3DSO.ai, the platform offers autonomous AI optimization and incorporates Ansys' physical analysis capabilities for power, thermal, and signal integrity, aiming to provide a complete solution from architecture to sign-off.

Cadence has introduced the Integrity 3D-IC platform, with its standout advantage being system-level multi-physics analysis and cross-platform collaborative design capabilities. The platform is deeply integrated with the company's Innovus (digital implementation), Virtuoso (analog design), and Allegro (packaging/PCB) tools, utilizing Celsius and Sigrity solvers to provide thermal and electrical performance sign-off support for the full chip-packaging-circuit board co-analysis chain.

Siemens EDA's layout (positioning) focuses on its Xpedition Package Designer and Innovator3D IC solution suite, establishing an advantage in verification sign-off with its industry-standard Calibre series tools. In particular, tools like Calibre 3DStress are dedicated to addressing issues such as warping and deformation caused by thermomechanical stress in 3D architectures.

Among domestic vendors, Empyrean Technology released its advanced packaging design platform, Empyrean Storm, in July.

According to reports, the platform supports cross-process packaging layout data import and design editing, deeply adapting to current mainstream silicon interposer and organic RDL processes. It enables large-scale automatic routing for multi-chip communications protocols like HBM and UCIe, completes DFM layout post-processing such as dummy filling to ensure mass production, and incorporates seamlessly integrated cross-process physical verification Argus, ensuring layout correctness through DRC/LVS checks. With these capabilities, Storm can handle large-scale, high-density interconnection routing and complex layout demands between multiple chips.

Xipei Semiconductor's Metis 2.5D/3D advanced packaging SI/PI simulation platform enables system-level signal integrity (SI) and power integrity (PI) simulation analysis. Additionally, its PIDC (power integrity DC) simulation flow can quickly evaluate voltage drop and current density hotspots across entire chiplets and 3DICs.

Meanwhile, the company's Hermes electromagnetic simulation platform offers comprehensive 3D structure editing and 3D component encrypted model functions, supporting full-spectrum electromagnetic simulations for any 3D structure, from chips, packaging, circuit boards, cables, connectors, to antennas.

03 Hybrid Bonding: Key Equipment

In the equipment sector, hybrid bonding-related equipment is particularly crucial.

Hybrid bonding is an advanced packaging technology for inter-chip connections, encompassing both wafer-to-wafer and chip-to-wafer bonding forms. Its core lies in achieving connections through direct contact between metal pads and surrounding oxides, without any filler materials like solder. By directly bonding metal and dielectric layers between chips, this technology provides high-density, low-power interconnection solutions for applications like high-performance computing, AI, and memory chips.

BESI from the Netherlands is currently the market leader in hybrid bonding equipment, holding a dominant position. The company has accumulated over 100 orders and delivered its first batch of equipment with 100-nanometer precision in 2024, with plans to achieve 50-nanometer precision by the end of 2025. Another global equipment giant, ASMPT, has also made significant progress, delivering its first hybrid bonding equipment to a logic chip customer in the third quarter of 2024 and securing application orders for next-generation HBM, with expected delivery in 2025.

Korean equipment vendors are particularly active in this field. Hanmi Semiconductor, a leader in the thermal compression bonding (TCB) market, has announced an investment of 100 billion KRW in R&D and production of hybrid bonding technology, with plans to launch related equipment by the end of 2027. Meanwhile, LG Electronics has chosen to bypass TCB technology and directly enter the hybrid bonding track (arena), aiming to complete proof-of-concept by 2028 and has begun recruiting core technical experts. Additionally, Hanwha Semiconductor Technology is collaborating with SK Hynix to develop its second-generation product, scheduled for launch in early 2026.

According to a Hua'an Securities research report, China's hybrid bonding equipment market is gradually rising, with vendors like PIOTECH and Micro-Tech slowly layout (positioning) in hybrid bonding equipment and making gradual breakthroughs in key technologies, expected to increase their market share in the coming years.

PIOTECH has established its 3D integration bonding equipment business through its controlled subsidiary, PIOTECH Bonding Tech, forming a complete product matrix of hybrid bonding, fusion bonding, and supporting metrology and inspection equipment. Multiple devices have passed client verification and achieved shipments, applied in advanced memory, logic chips, and image sensor fields. The company's wafer-to-wafer bonding product, Dione 300, is the first domestically produced hybrid bonding equipment, with its W2W/D2W hybrid bonding pre-surface treatment and bonding products receiving repeat orders.

Recently, Micro-Tech stated that it has layout (positioned) itself in semiconductor bonding processing equipment, covering key equipment like hybrid bonding, thermal compression bonding, temporary bonding, and laser debonding, aiming to serve advanced packaging, compound semiconductors, and new display sectors (with end applications in AR glasses and automotive use). Multiple sets of the company's bonding equipment have been shipped to clients for verification. On July 15, Micro-Tech announced the successful delivery of its self-developed fully automated wafer-level hybrid bonding equipment to a new domestic client.

04 In-Memory Computing: The Future Trend?

In-memory computing technology aims to address the "von Neumann bottleneck" in traditional computing architectures. In this architecture, frequent data movement between independent memory and computing units leads to significant latency and power consumption, particularly prominent in data-intensive applications like AI. To achieve in-memory computing, 3D-IC technology provides a critical physical foundation. Through 3D packaging processes, memory chips like high-bandwidth memory (HBM) can be vertically stacked with logic computing chips, greatly shortening data transmission paths and increasing bandwidth, thereby effectively reducing the energy consumption and latency of data movement and paving the way for in-memory computing architectures.

International semiconductor vendors are actively layout (positioning) in-memory computing technology and have launched commercialized products in various application scenarios. In the end-side consumer electronics sector, MediaTek has integrated an in-memory computing architecture into its Dimensity 9500 flagship smartphone chip. The company adopts a parallel technical path in both digital and analog domains, with the former based on SRAM for mobile tasks requiring high real-time performance and the latter targeting edge scenarios with extremely high energy efficiency requirements.

In the cloud AI inference sector, US startup d-Matrix has demonstrated its application. The company's Corsair accelerator employs digital in-memory computing (DIMC) technology, tightly integrating large-capacity SRAM and LPDDR5X memory units with computing functions through a chiplet architecture. Its design goal is to perform matrix operations directly near the memory to address the excessive energy consumption from data movement during large AI model inference.

Among domestic enterprises, Houmo Intelligence released its end-side AI chip, "Manjie M50," based on in-memory computing technology this year. The chip can provide up to 160 TOPS of computing power on a single chip and supports a maximum memory configuration of 48GB and a bandwidth of 153.6GB/s. In terms of actual performance, Manjie M50 can currently achieve an inference generation speed of over 25+ Tokens/s for large models with 7B/8B parameters and has completed adaptation for the DeepSeek 70B large model. Theoretically, the chip can also support models with hundreds of billions of parameters.

As one of the earliest domestic companies to layout (position) in-memory computing, Witintech's mass-produced WTM2101 chip is the world's first in-memory computing voice chip based on NOR Flash, focusing on end-side low-power voice interaction scenarios. Currently, there is the WTM2 series for high energy efficiency scenarios and the WTM-8 series, a new generation of computational vision chips for low-power, high-computing scenarios, supporting Linux, AI super-resolution, frame interpolation, HDR, detection, and recognition.