On January 2, 2026, Biren Technology rang the bell at the Hong Kong Stock Exchange: the issue price was set at the maximum of HK$19.60; the opening stock price surged by +82.14%, at one point pushing the market capitalization past HK$100 billion during the session, and closing at around HK$82.5 billion; public subscription was oversubscribed by 2,347 times, reflecting strong retail investor enthusiasm.

The bullish market sentiment is inseparable from its scarcity as the first GPU company listed on the Hong Kong Stock Exchange, with the label of 'domestic NVIDIA' making it a hot target for capital. However, setting aside these accolades, we care about whether Biren is truly a high-quality company.

1. Journey: A Company That Grew on the Entity List

To understand Biren, we must comb, sort out, organize, arrange, streamline (chū lǐ, 'trace') its development journey, which itself is a 'bitter history' of the domestic chip industry.

1) 2019-2022: Primary capital doubles down on chip localization. Founded in 2019, the company emerged at a time when the U.S. placed Huawei on the Entity List and HiSilicon faced supply cuts, prompting the primary market to focus on 'chip localization' as an investment theme. The vacant domestic GPU market urgently needed startups capable of shouldering the grand narrative of 'domestic NVIDIA' without letting investors' money go to waste. Against this backdrop, founder Zhang Wen stepped onto the stage with an impressively diverse background.

With an engineering degree from Jiao Tong University, legal and business studies abroad, early career as a lawyer, and later transition to investor, Zhang only truly entered the semiconductor industry in 2011. He assembled a GPU startup team composed of top technical experts from AMD, Qualcomm, Huawei HiSilicon, and other leading firms.

With a compelling narrative, talented team, vision, and scarcity (at a time when Moore Threads and MetaX had not yet been founded), it was no surprise that capital flocked to the company. Between 2019 and 2021, the company completed seven rounds of financing, raising a total of RMB 4.7 billion, with a post-Series B valuation exceeding RMB 11 billion.

2) 2022-2024: From stunning product debut to passive production line 'upgrades.' In August 2022, the highly anticipated Biren officially launched its BR100/104 products, with the BR100 as its flagship, positioning it as having 'over 3x the computational power of the A100 and performance approaching the unreleased H100.' Concurrently, it developed the proprietary BIRENSUPA software stack, emphasizing the narrative of a Chinese version of the H100.

However, a closer look at the product specifications—TSMC 7nm process, CoWoS-S packaging, HBM2e—allowed astute investors to anticipate what would happen next. Two months later, the BIS issued new export control regulations ('ECCN 3A090'), triggering restrictions based on the BR100's parameters.

Four months later, in January 2023, Biren suddenly achieved mass production of the BR106. Where did this model come from? Dolphin Research speculates that the BR106 is a 'down-spec' iteration of the BR104, designed to circumvent the new regulations. Initially, it was likely still produced by TSMC, but after being placed on the Entity List, production shifted domestically.

Note: In October 2023, Biren was specifically targeted for sanctions, with the BIS adding it and 12 other Chinese entities to the export control Entity List and attaching 'Footnote 4,' meaning foundries must obtain a license before delivering products to these customers. TSMC's manufacturing channel was completely closed off.

From being sanctioned to achieving domestic production line mass production, Biren's speed was commendable. However, before and after the two rounds of sanctions, co-founders Jiao Guofang and Xu Lingjie departed. Faced with a high-valuation company that had experienced flagship product failures, product down-specing, forced production line 'upgrades,' and startup team attrition, the 'halo' around the 'domestic NVIDIA' began to fade in the capital markets.

3) 2024-Present: Commercialization kicks off

Rhythm was only fully restored in 2024. Among its products, the BR166, a high-computational-power dual-chip configuration within the current 100-series lineup and the current revenue mainstay, only began mass production in August 2025.

Currently, the BR100 product line includes three models: the single-chip BR106, the dual-chip BR166 (revenue mainstay), and the IoT chip BR110. Overall, these three products were all developed in 2022.

For Biren and other domestic chip startups, value restarted in the first half of 2025 when the H20 was banned. Even after its potential lifting, and even if the H200 were approved, domestic cloud giants' budgets would still be rigidly allocated to domestic chips. The market has begun to firmly recognize that 'domestic chips' have become a 'must-have' under the import substitution trend.

With this powerful new narrative, Moore Threads and MetaX listed on the STAR Market, while Biren and Illuvium listed on the Hong Kong Stock Exchange, with Enflame Technology also set to go public soon. Amid this revaluation of domestic chip value, what sets Biren apart from its peers? How long can it ride the industry's tailwinds? Where are its future core growth drivers? Let's continue the analysis.

2. Short-to-Medium Term: 'Shipments' Reign Supreme

Currently, the logic behind domestic chip performance is simple: supply is king. Whoever can scale up chip shipments will secure a share of cloud capital expenditure budgets. With NVIDIA's GPU market share in China plummeting from nearly 100% to near-zero and the AI industry entering the Agent era, further exploding demand, the resulting supply-demand mismatch is enormous.

According to Dolphin Research's rough estimates, this gap may only begin to close gradually by 2028-2029, with a demand-driven era arriving only after 2029. The demand shortfall in 2026 is expected to be around 40-50%.

1) Supply: Advanced production capacity is scarce

It is widely acknowledged that domestic GPUs lag in single-core performance, typically falling one to two generations behind NVIDIA/AMD. The common domestic approach is to stack and interconnect chips at various levels (Die-Die/GPU-GPU) to bridge the gap, but this cannot fundamentally eliminate the process technology gap with overseas foundries. Currently, upstream constraints remain in areas such as photolithography and EDA for domestic AI GPUs:

- EDA: Domestic EDA leader Empyrean holds about 15.7% of the domestic market but only 2-3% globally and has yet to offer a full digital IC design suite. Additionally, the U.S. strictly regulates exports of advanced-process (7nm and below) EDA software to China.

- Photolithography equipment: China still relies on ASML DUV imports, accelerating procurement in 2025 to hedge against escalating controls, while EUV export controls remain the critical bottleneck.

- Foundry services: Due to equipment restrictions, domestic advanced processes (N+2: 7nm; N+3: 5nm) represent scarce capacity. Currently, SMIC is the primary provider, with most domestic GPU designers vying for its capacity. Another player, Hua Hong Semiconductor, is only producing at small scale, with yield rates and capacity yet to be verified.

Limited by capacity, some GPU vendors are forced to use the N+1 process (first-generation 7nm), but chip performance is highly correlated with process advancement—a last resort (wú nài zhī jǔ, 'move made out of necessity') under capacity constraints.

Thus, Dolphin Research roughly estimates total supply based on 'wafer capacity → AI capacity allocation → manufacturing yield → dies per wafer → packaging yield → total Die supply.'

2) Demand: AI agent adoption explodes

On the demand side, import restrictions on AI logic chips have made localization a necessity. However, as domestic products currently struggle to meet training demands, we primarily assess inference chip requirements here.

a) Internet giants like Alibaba, ByteDance, and Tencent;

b) Foundation model developers like DeepSeek, MiniMax, and Zhipu, which continuously consume tokens and have such large single-demand volumes that they can bypass cloud providers to directly request chips.These players benefit primarily from structural growth in inference demand, with leading firms' foundation models pushing daily token consumption past ten trillion. This segment is the main demand driver.

c) Sovereign AI players, including telecom operators, state-owned enterprises, and local governments, whose demand stems from national AI infrastructure construction, data sovereignty, computing centers, and public sector applications.

Market demand is derived from domestic AI spending plans, following the chain: 'customer AI/cloud Capex → exclude CSP overseas spending → × server share × AI server share × accelerator component share → AI GPU market size TAM → /ASP/computational power to derive card volumes → GPU Die count → CPU/GPU ratio → CPU Die count → total Die demand.'

Overall estimates suggest around 4.2 million AI chips will be needed in 2026, but supply will only reach 2.6 million, leaving a visible gap.

3. Short Term: How Strong Is Biren's Capacity Lock-In Ability?

To gauge Biren's short-term revenue growth potential, we must analyze whether it can secure sufficient capacity to support scaled shipments. According to our research, given current foundry capacity constraints, manufacturing capacity is allocated under a 'quota system' that moderately favors growing vendors to avoid over-concentration among a single dominant player.

Dolphin Research argues that this planned quota system benefits Biren, a relatively 'second-tier' chip vendor (as explained below), because quota allocations emphasize strategic distribution over fully market-driven pricing.

1) Basic threshold for quota allocation: software compatibility

Current hard criteria for quota allocation heavily emphasize Day 0 model compatibility, testing software capabilities. We observe that domestic AI chip firms are collaborating closely with domestic AI model companies to proactively achieve Day 0/deep model compatibility.

Currently, these emerging core chip vendors all claim Day 0 compatibility upon model release, though actual runtime smoothness may vary. The image below shows Biren's compatibility with mainstream large models, meeting the baseline threshold.

Now, examining the 'soft' conditions for locking in capacity: financial backing.

- Sovereign funds: Hygon and Cambricon have strong state-owned (central) backing and are expected to benefit first from SMIC's advanced capacity (with Huawei remaining the top priority). Meanwhile, the Shanghai government supports three local vendors—Biren, MetaX, and Enflame—so Biren is not the 'sole favorite.'

- Industry players: Enflame and Cambricon secured Tencent and Alibaba as major investors before their IPOs, respectively, ensuring more demand-side security than Biren, which currently lacks strong ties to a major partner.

While Biren lacks unique 'deep connections,' it can still secure capacity because:

First, for local governments, all vendors are important, and their involvement ensures second-tier players can obtain capacity shares superior to purely market-driven outcomes.

Secondly, Hua Hong International (with shareholders Shanghai SASAC (51.59%), Shanghai Guosheng (18.36%), Shanghai International Group (18.36%), and Shanghai Instrumentation (11.69%)) appears on Biren's placement list as a 'close associate of existing minority shareholders' (albeit with a mere 0.13% stake), meaning that the wafer foundry is its shareholder.

Investigations also confirm that Biren has begun engaging with wafer foundries other than SMIC and has prepared two sets of product solutions. We believe that as Hua Hong's 7nm process gradually ramps up production, Biren will gradually secure wafer supply in line with Hua Hong's capacity expansion.

2) Why might yield become a constraint?

Despite the aforementioned positives, the fact remains that SMIC (the major player in advanced capacity) does not prioritize Biren in its production scheduling. We assess that future product supply will primarily come from Hua Hong. However, Hua Hong's advanced process is still in the early stages of production, with capacity yet to ramp up.

This process is achieved through DUV multi-patterning rather than EUV, resulting in relatively low chip yield and energy efficiency, which in turn hampers shipment capabilities. This represents the most critical short-term risk factor.

4. Long-term: Can Biren outperform in the long run?

In the long term, competition hinges on each manufacturer's product strength, which currently can be divided into three major dimensions:

a. Single-chip capability: core parameters and iteration speed;

b. Chip software-hardware integration and ecosystem capabilities;

c. System-level solution delivery capabilities.

Among domestic players, except for HiSilicon, which has relatively strong capabilities in delivering systematic products, others are still focused solely on chip development. Looking specifically at Biren:

1) GPGPU-based hardware systems;

2) Software platform BIRENSUPA;

1) GPGPU-based hardware systems

In mainstream AI computing chip types, there are three paths: ASIC, FPGA, and GPGPU. The company primarily focuses on self-developed GPGPU chips, accelerator cards, and whole-machine servers, adopting a Fabless model that outsources wafer fabrication and packaging/testing to third-party foundries.

Currently, Biren has mass-produced three GPGPU chips—BR106, BR110, and BR166—implemented via PCIe boards and OAM modules. Key specifications of its products are summarized as follows:

Following the discontinuation of BR100/104, the company no longer discloses specific comparable parameter specifications for its products. According to Everbright Securities, the performance of its single-chip models (BR100/BR104/BR106) is outstanding among domestic chips, supporting a +273% YoY growth in overall chip shipments. However, these figures reflect data from previous product generations. Dolphin Research is more focused on the flagship products BR166 and BR20X.

a) Is BR166 competitive?

BR166 is essentially a dual-chip version of BR106, doubling its computing power while retaining the same architecture as the original BR106, which itself was based on the 2022 BR100.

According to the prospectus, 'We utilized chiplet technology to integrate two BR106 bare dies and four DRAMs into a single package... The D2D (die-to-die) bidirectional bandwidth between the two BR106 bare dies can reach up to 896GB/s.' The architecture (shown below is the BR100 architecture, which BR166 continue [continues with] except for disclosing DRAM as its memory) is as follows:

At the time, Biren demonstrated considerable architectural innovation for AI computing scenarios, pairing high computing power with an exceptionally large on-chip L2 cache (H100 has only 50MB, while BR100 boasts 256MB).

In terms of microarchitecture design, we know that NVIDIA's SM is its basic scheduling granularity. Similarly, Biren's SPC contains smaller EU units that support dynamic scheduling granularity combinations of 4/8/16 EUs, enabling finer-grained resource reuse based on workload characteristics.

In terms of computing power (matrix throughput), each EU is configured with one T-Core (1 SPC has 16 T-Cores for parallel computing); under Hopper architecture, a single SM has 4 Tensor Cores. This approach is better suited for chiplet solutions under domestic yield conditions.

Currently, the lack of native support for FP8 & FP4 data formats is its biggest drawback. Without low-precision data formats, it faces inherent disadvantages in efficiency for large-model training and inference scenarios, where these formats are now widely used.

Among domestic peers, since the BR100 is a 2022 product, its single-chip computing power is still acceptable. However, it has been surpassed by competitors in areas such as inter-chip interconnectivity, memory bandwidth and capacity, and computational precision. Ascend 910C basically targets the H100, while Moore Threads/Enflame products now offer comprehensive performance between H100-H200 levels. BR166's product strength appears somewhat inadequate.

We observe its downstream partners (yellow background indicates delivery) for confirmation. Biren's products are primarily shipped to sovereign AI projects such as operators and computing centers, lacking large-scale orders from CSPs. A major reason is that CSPs' deployments focus on inference demands, which currently require large memory capacities and strong connectivity. Biren's current product line is relatively weak in these areas, making BR166 not a particularly competitive product overall.

Besides the potential factor of inadequate product strength, we have already reviewed Biren's tortuous development history in Section 1. Geopolitical factors have introduced supply chain uncertainties, preventing the company from proving to internet customers its ability to provide long-term, stable, and large-volume supply.

However, given the current overwhelming demand, these issues are not major problems in the short term. Financial data from three dimensions—orders in hand, advance payments, and production preparation—sideways confirm the certainty of downstream demand for Biren:

- Orders in hand: According to the prospectus, the total value of outstanding binding orders under framework sales agreements and sales contracts reaches RMB 822 million, providing a solid foundation for future revenue.

- Contract liabilities: Contract liabilities reached RMB 77 million by the end of 2025, with customers already locking in orders through advance payments.

- Inventory: Net inventory reached RMB 949 million by the end of 2025, up over 500% YoY. Structurally, raw materials (RMB 386 million) and work-in-progress (RMB 431 million) accounted for approximately 85% of the total, indicating that inventory expansion stems from confirmed orders.

b) What about BR20X?

While BR166 lacks outstanding competitiveness, standing at the 2026 milestone and considering a typical 3-4 year product iteration cycle, the next-generation flagship BR20X series is imminent. The timeline is as follows:

(1) BR20X series: Currently undergoing physical design and tape-out verification, with commercialization planned for Q4 2026. The company will enhance single-chip capabilities while accelerating the development of super-node systems.

(2) Product parameters: As the next-generation flagship product with a fully domestic supply chain to avoid restrictions, its evolution aligns with our expectations:

- FP8 & FP4 will be equipped in the BR20X series to accelerate compatibility with large-model training and inference demands;

- Deliver stronger computing power;

- Feature larger and faster memory, higher-speed interconnect bandwidth, and super-node system design.

In terms of specific specifications, we estimate that BR20X will target NVIDIA's H200. Without public information on exact parameters, Dolphin Research provides the following estimates for BR20X based on reference benchmarks and research findings:

The new product primarily addresses the shortcoming of insufficient memory capacity, though connectivity still requires improvement. Overall, by addressing previous weaknesses, the new product should be capable of securing orders from major players. The key challenge remains the yield rate during the ramp-up of the new production line.

2) Software platform BIRENSUPA

While hardware vendors are exploring various approaches to narrow the technological gap with NVIDIA, in software, CUDA represents an insurmountable barrier for all vendors. CUDA's strengths need no elaborate explanation: its moat built through first-mover advantage, deep hardware and software [hardware-software] integration enabling ultimate [ultimate] performance optimization and software compatibility, and a rich toolkit library.

Domestic vendors generally follow two routes in response. First, adopting CUDA-compatible modes, such as Moore Threads' MUSA and Moore Elite's MACA, which they use as commercial selling points. Second, full-stack self-development, represented by Huawei's CANN and Cambricon's Neuware. The former has deeply bound sovereign orders through over five years of operator accumulation, while the latter has vertically cultivated recommendation system scenarios, securing commitments from leading CSPs like ByteDance. Biren initially planned to pursue a self-developed ecosystem.

BIRENSUPA exhibits significant shortcomings in terms of openness and software stack richness, with ecosystem development still in its early stages. It also faces frictional costs in engineering implementation. Research indicates that in complex scenarios, BIRENSUPA may still require manual modification of underlying IR code or suffer from relatively high compilation error rates. Synchronization delays in some communication libraries within thousand-card clusters also need optimization.

To address these gaps, Biren plans to allocate 40% of its IPO proceeds to optimize its software stack ecosystem. It has gradually provided comprehensive support for mainstream open-source frameworks such as PyTorch, vLLM, and SGLang, enabling access to the vast existing market built by the CUDA ecosystem and reducing customer migration costs.

In the short term, Biren's shift from a self-developed to a compatible ecosystem is reasonable. Its scale, customer structure, and commercialization capabilities cannot support continued investment in self-development. Ultimately, customers evaluate solutions based on cost-effectiveness, which reflects a combination of hardware and software.

However, from a longer-term perspective, compatibility does not inherently create competitive barriers. In an optimistic scenario, Biren may excel as an intermediary layer compared to other vendors. However, if Biren fails to establish differentiation in software usability, stability, and third-party ecosystem development, it may quickly fall into homogeneous competition.

3) Super-nodes: Is there a solution?

Biren's products are delivered in the form of GPU clusters/super-nodes, but its value contribution in delivery solutions is limited to the GPU segment. The value of interconnectivity, switching, and whole-machine integration is ceded to upstream and downstream partners such as Lightelligence and ZTE.

In the industry, except for Huawei, which has achieved full-stack self-development, most domestic vendors are still in the early stages of self-developed interconnectivity layouts (having only achieved self-developed inter-card interconnect protocols). They collaborate with upstream and downstream vendors in switch chips (benchmarked against NVSwitch) and whole-rack system integration.

Currently, research and development efforts are concentrated on computing chips and software stacks, with interconnectivity yet to become a differentiating factor. However, interconnectivity technologies hold significantly amplified value in the AI era. Scale-up/out/across capabilities will determine the model size that a single node can support.

We believe that companies capable of delivering 'turnkey' solutions first will benefit from building long-term ecological barriers. Biren holds no fundamental difference from its startup peers in this regard.

5. From a comprehensive perspective, among its peers, Biren's main differentiation lies in its single-chip capability. However, the importance of the core single-chip in current inference chips is actually declining, with memory and connectivity in the computing power module becoming increasingly crucial. There is no differentiation in systematic hyper-node delivery solutions, as all are still in their early stages. Additionally, in terms of the critical software ecosystem, Biren is not particularly prominent among its peers.

However, its strength lies in the fact that, under the 'production capacity quota' model, it has the potential to be a strong contender and continues to receive policy support. Its ability to list on the Hong Kong Stock Exchange is also a reflection of official endorsement. Moreover, in the short term, the commercialization of the BR 20X is imminent, providing an excellent baton for the release of future performance.

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