This year's WAIC 2026 was dominated by discussions of high-performance cloud AI chips. However, amid the buzz surrounding large chips, changes are also underway with edge AI chips. Manufacturers are beginning to consider how to bring more powerful AI capabilities down to the edge. After two years of rapid advancement in large models, edge AI chip manufacturers have collectively "leveled up" overnight: 3D stacking, compute-in-memory, and counterattacks from the edge to the cloud. These three major trends intertwined at WAIC 2026 to form a new industrial landscape that may redefine the ultimate form of AI computing power.

01 SoC and Coprocessors: Two Forms of Edge AI Chips

Looking across WAIC 2026, the most immediate impression is that edge AI chips are splitting into two worlds.

On one side is the SoC (System-on-Chip) route. Cixin Technology's P1 chip (CP8180) integrates a 12-core CPU, a 10-core GPU, and a 3-core self-developed NPU, delivering an overall computing power of 45 TOPS. It's like compressing a complete "AI computer" into a single chip. The advantage of this "fully integrated" solution lies in its complete ecosystem: customers can directly run Linux or Android systems (even Windows) without the need for an additional main control chip. Rockchip's RK3588 is another familiar face in the edge space, with its 6 TOPS NPU finding its way into a wide range of AIoT applications, from tablets to in-car cockpits, from TVs to robots.

On the other side are edge coprocessors, a more active track at WAIC 2026. This includes Guangyu Xinchen's TC1020 chip, Houmo Intelligence's Manjie M50 chip, Rockchip's RK1828/1820 chips, Weiheng Technology's Fuguang LPU, and Xindongli Technology's RPP chip. None of these can independently run an operating system; instead, they act as "AI accelerators" that work in tandem with a main control chip via standard interfaces. "Coprocessors don't run operating systems; they accelerate AI inference. You can think of them as NPU," explained a Rockchip engineer. "They need to be paired with a main control chip; RK3588+RK1828 is our golden combination." This "main control + coprocessor" architecture allows users to smoothly upgrade computing power through interfaces like PCIe without overhauling their existing systems.

Coprocessors are also becoming more diverse in their physical forms. PCIe×16 slots (such as Houmo Intelligence's Limo LM5070), PCIe×4 slots (such as Houmo Intelligence's Limo LM5030), M.2 interface modules (such as Xindongli Technology's AzureBlade M.2 accelerator card), USB connections, and even SO-DIMM memory slot form factors. Houmo Intelligence even showcased a dual-chip architecture accelerator card connected via two side-by-side M.2 interfaces (Houmo Intelligence's Liqing LQ50 Due M.2 card), with two M50 chips interconnected via the C2C protocol. This "stackable small computing power" approach is reshaping the hardware landscape of edge AI. Computing architectures are also flourishing, with Rockchip, Guangyu Xinchen, and Houmo Intelligence betting on NPUs; Suaneng deep cultivation (Suaneng delving deep into) the TPU route; Xindongli Technology opting for GPGPUs compatible with the CUDA ecosystem; and Weiheng Technology focusing on LPUs.

Behind this divergence in routes lies different trade-offs between "flexibility" and "computing power density" for edge scenarios. A Rockchip staff member admitted, "Coprocessors are decoupled from the main control. If a customer's system is already developed but lacks computing power, they can simply plug in a coprocessor box without affecting the main control's operations."

02 3D Stacking "Trickles Down": Breaking the Memory Wall for Edge Chips

At WAIC 2026 this year, not only are cloud chips massively adopting 3D stacking technology, but edge AI chips are also following suit. This technology is making its way down to the edge at an unexpected pace.

Rockchip

The RK1828 claims to be the "industry's first mass-produced 3D-stacked edge chip," with DRAM directly stacked on top of the NPU. Storage capacity options include 2.5GB or 5GB, with a theoretical bandwidth of approximately 1TB/s. In a live demonstration, a TV equipped with the RK1828 was converting ordinary video footage into 3D in real-time; inference speed for a 3B large model exceeded 100 tokens/s, while the RK3588 could only manage a dozen tokens/s for the same model—an improvement of nearly an order of magnitude. A Rockchip engineer stated, "3D stacking has a huge impact on this. Large models require massive amounts of data movement, which previous edge chips simply couldn't handle."

Guangyu Xinchen

Globally premiered the TC1000 series of edge high-performance 3D-stacked near-memory computing low-power large model inference chips. Leveraging a self-developed 3D-stacked near-memory computing architecture + compute-in-memory technology + storage hierarchical technology, it achieves a 10x leap in equivalent bandwidth and consumes only 1/3 the power of traditional solutions for the same computing power, breaking through industry performance ceilings: it has achieved ultra-high-speed inference of 300 tokens/s for a single-chip 3B model and supports high-performance operation of 35B-scale large models. The currently displayed TC1020 chip delivers 56 TOPS@INT8 computing power, 5/10GB of storage capacity, and a decoding speed of >200 tokens/s for 7B LLM models, with product power consumption of only 8-15W.

Weiheng Technology

Although the product has not yet been taped out, the specifications for the Fuguang Englight-LPU chip have been planned, delivering 256TFLOPS of computing power. It adopts a 3D+2D heterogeneous memory architecture, with 3D-stacked memory reaching 10-40GB and bandwidth of 5TB/s, along with 2D extended storage of 8-64GB and bandwidth of 136GB/s. A single chip can support 200B large models.

The collective explosion of 3D stacking in 2026 fundamentally stems from the industry's consensus on the bandwidth bottleneck in Transformer inference. A Guangyu Xinchen technician put it bluntly: "When doing Transformer inference, the bottleneck is bandwidth, not computing power. No matter how fast your computing core is, if data can't be moved fast enough, it's useless." However, 3D stacking is not without its costs. Built-in DRAM drives up chip costs, and capacity remains limited—5GB is still insufficient for models above 35B. To address this, companies are adopting "external" strategies: Guangyu Xinchen has reserved LPDDR5 interfaces on its chips for external memory expansion; Rockchip is planning multi-chip cascading functions for its next-generation coprocessors, allowing multiple chips to be connected to break the 10 billion parameter barrier. A notable industry consensus is emerging: 35B parameters represent the "sweet spot" for edge Agents. A Guangyu Xinchen technician explained, "Agents below 35B don't work; their capabilities are insufficient. 35B is now seen as a reasonable size for running edge Agents."

03 Compute-in-Memory Steps Out of the Lab: SRAM, MRAM, and "True CIM"

If 3D stacking addresses "moving data fast," then compute-in-memory (CIM) aims for "not needing to move it at all." At WAIC 2026, CIM is no longer just a concept but a technology that has been taped out and even mass-produced.

Houmo Intelligence is the most aggressive practitioner in China. Its M50 chip has already entered mass production, using SRAM as the core for compute-in-memory by embedding computing units directly into the memory array. This is not simple near-memory computing (which 3D stacking falls under) but circuit-level in-memory computing, where computing units are placed directly inside the SRAM, with results stored locally. "We're the first in China to do digital compute-in-memory," a Houmo Intelligence staff member asserted with confidence. Houmo has even defined a custom "bFP16" precision format to strike a new balance between performance and accuracy. The CIM architecture also delivers high energy efficiency: "During inference, especially in the decoding stage of large models, CIM eliminates the overhead of data movement," the Houmo staff explained. "Our chip runs at just 10 watts but delivers 160 TOPS (INT8). Traditional GPUs have too high an IO cost."

Hanxu Technology has chosen a different technical route: MRAM compute-in-memory. Incubated by Peking University's Applied Magnetics Center, the company used Samsung's 8nm process for tape-out, employing MRAM (Magnetic Random Access Memory) as the computing medium and SRAM as the cache. MRAM's advantage lies in its non-volatility (data is retained even when powered off). "Traditional GPUs have separate memory and computing units; ours are truly integrated," emphasized a Hanxu Technology staff member.

04 AI NAS: The "Greatest Common Denominator" for Edge Chips

The evolution of technology and products must ultimately land in specific scenarios. When it comes to application deployment, WAIC 2026 provided an unexpected answer: AI NAS. Almost every edge chip manufacturer's booth featured AI network storage devices. Cixin Technology partnered with Meigo, Suaneng launched products with ecosystem partners, and Rockchip supplied Green Union/Ruisha... AI NAS suddenly became the "greatest common denominator" for edge AI. The reason lies in NAS's role as a local data storage center. When combined with AI computing power, it enables intelligent organization of local photos/videos, natural language retrieval, and AI processing with privacy protection—all without uploading data to the cloud.

AIPC is another major deployment scenario. Cixin Technology's P1 chip is used in Lenovo's mini-host (approximately 2,500 yuan after national subsidies), supporting the simultaneous operation of over 20 intelligent agents. Moreover, Cixin Technology is the "world's first ARM architecture SoC manufacturer that can directly install the standard version of Windows ARM system" without requiring special adaptation from Microsoft. Suaneng and Rockchip are also making strides in the trusted computing notebook space, adapting to domestic operating systems.

Embodied intelligence is pushing the boundaries of imagination for edge chips. Cixin Technology collaborated with Tianshu Zhixin to launch a robot controller based on NPU for object recognition and grasping. Hanxu Technology's MRAM chip was adopted by Yinhe General for the robotics sector.

05 Blurring Boundaries: Edge Manufacturers' Path to the Cloud

The most intriguing trend at WAIC 2026 is the blurring of boundaries between edge and cloud. Edge chips are beginning to access the cloud through distributed architectures, forming servers.

Cixin Technology started with edge SoCs and developed an array server that can accommodate up to 60 SoC chips. According to introductions, each server integrates 60 small boards, with each board featuring a single P1 (CS8180) chip, 48GB (4*12GB) of LPDDR5X memory (optional), and a system SSD, forming a "minimal computing unit." The entire machine is managed by a single BMC processor. "Traditional servers use one large CPU for big tasks; we break it down into 60 small units, each handling its own small tasks," explained a Cixin Technology technician. A single P1 chip can run 6-7 instances of Honor of Kings or 16 instances of Douyin (TikTok). With 60 chips combined, the entire machine can support 360 concurrent game sessions or 900 Douyin live streams. This means edge chips are counterattacking the cloud with distributed architectures. In scenarios like cloud gaming, cloud phones, and Android cloud servers, where numerous lightweight, concurrent computing tasks exist, expensive single Xeon CPUs are unnecessary. Instead, low-cost, low-power edge SoCs stacked together are more suitable. Cixin Technology revealed that such array servers previously relied on competitor solutions but have now "mostly switched to our company."

Xindongli Technology's GPGPU also straddles both ends, with M.2/PCIe small cards for the edge and a board accelerator card integrating 12 AE7100E chips for the cloud, compatible with the CUDA ecosystem. By loading 8 such accelerator cards into a high-density server, it can support deployment of large models with 400B to 1.6TB parameters, already implemented in medical genetic sequencing solutions. This distributed architecture of small chips provides a new solution for edge chips to access the cloud.

Suaneng represents another typical path from edge to cloud. This company, which has deep cultivation (delved deep into) the edge TPU space for nearly a decade, went low-profile in 2024 due to sanctions. However, at WAIC 2026, its cloud product line made a full comeback: the OpenClaw Lobster all-in-one machine, equipped with 4 OAM modules and a Hygon CPU, delivers 1P computing power (FP8); the cloud TPU accelerator card has iterated to the second generation, with the third generation coming soon; the world's earliest server-grade RISC-V processor has also been deployed in clusters at Shandong University. "We started at the edge, but we're targeting both cloud and edge," a Suaneng staff member stated. Under the large model trend, demand for cloud computing power is clearly stronger than at the edge, which is the fundamental reason edge manufacturers must extend upward.

This era is no longer defined by simply comparing TOPS figures but by systemic competition involving architectural innovation (3D stacking, compute-in-memory), form factor innovation (standardized interfaces for coprocessors), and scenario innovation (edge-cloud-edge convergence). 3D stacking proves that edge devices can run large models; compute-in-memory demonstrates that low power consumption can support high computing power; and 60-SoC arrays show that edge chips can handle cloud tasks. Of course, challenges remain real: DRAM price hikes squeeze profits, advanced manufacturing process foundry access is limited, killer applications are still being cultivated, and ecosystem adaptation is far from complete.